74.6.4.1 SDMMC I/O Calibration

The device embeds I/O calibration cells for SDMMC0, SDMMC1 and SDMMC2. The purpose of this block is to provide to e.MMC/SD I/Os an output impedance reference to limit the impact of process, voltage and temperature on the drivers output impedance. The impedance control is required at high frequency in order to improve signal quality.

The calibration cell provides input pin SDMMCx_CAL loaded with a 20 KΩ RZQ resistor for 1.8V memories and a 16.9 KΩ resistor for 3.3V memories. In the above figure, CZQ is not mounted.

• According to the e.MMC specification, the output impedance calibration is required for HS200 and HS400 modes (1.8V) whereas it is not for other modes (3.3V).
• In addition, according to the SD specification, the output impedance calibration is required for 1.8V signaling in SD UHS-I whereas it is not for 3.3V signaling. When the interface needs to operate at both 1.8V and 3.3V, RZQ has the 1.8V value (20 KΩ) .

The following table shows the values to program in the SDMMCx_CALCR.CLKDIV field with respect to MCK1 clock frequency.