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26.3.12 PTG Step Queue n Pointer
Register (n = 0-7)
Note:
These bits are read-only when
the module is executing step commands. Refer to Table 26-5 Table 26-18. Register Bit Attribute Legend Symbol Description Symbol Description Symbol Description R Readable
bit HC Cleared by
Hardware (Gray
cell) Unimplemented W Writable
bit HS Set by
Hardware X Bit is unknown
at Reset C Write to
clear S Software
settable bit x Channel
number
Name: PTGQUEn Offset: 0x3530, 0x3534,
0x3538, 0x353C, 0x3540, 0x3544, 0x3548, 0x354C
Bit 31 30 29 28 27 26 25 24 STEP(4(n) +
3)[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16 STEP(4(n) +
2)[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 STEP(4(n) +
1)[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 STEP(4(n))[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bits 31:24 – STEP(4(n) +
3)[7:0]
PTG Command Step 4n + 3 bits(1,2) A queue location for
storage of the STEP(4n + 3) command byte.
Bits 23:16 – STEP(4(n) +
2)[7:0]
PTG Command Step 4n + 2 bits(1,2) A queue location for storage
of the STEP(4n + 2) command byte.
Bits 15:8 – STEP(4(n) +
1)[7:0]
PTG Command Step 4n + 1 bits(1,2) A queue location for storage
of the STEP(4n + 1) command byte.
Bits 7:0 – STEP(4(n))[7:0]
PTG Command Step 4n bits(1,2) A queue location for storage
of the STEP(4n) command byte.
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