23.4.3.1 Gated Timer Mode Clock Considerations

The timer may be using the prescaler for a slower timer increment rate. Note that the gated timer clock is routed through the prescaler. When using the prescaler, the prescaler will simply retain its current count value as the gate is low. Note that if the user writes the TMRx register, the prescaler will be reset. Using the prescaler will not affect the function or timing of the falling edge interrupt.

When the CPU goes into Sleep mode or Idle mode with SIDL bit = 1, the timer will stop incrementing. The timer module logic will resume the incrementing sequence upon termination of the CPU Idle/Sleep mode. If SIDL bit in TxCON register = 0, the timer will continue to operate normally.

The period matching function remains operational in gate mode operation. If the timer matches the period, the timer will reset, but the period match does not generate an interrupt.

Note: Gated Timer mode is overridden if the Timer Clock Source Select bit (TCS) is set to an external clock source, TCS = 1. For Gated Timer mode operation, the source must be selected (TCS = 0).