26.4.7.2 Configuration

The WDT is configured by setting the PTGWDT[2:0] bits (PTGCON[18:16]). The WDT counts the PTG clocks as defined by the PTG input clock selection and the PTGDIV[4:0] bits in the PTGCON register. For more information, refer to PTG Clock Selection. The WDT time-out count value is selected by using the PTGWDT[2:0] bits and is disabled when PTGWDT[2:0] = 0b000.

Note:
  1. The WDT is disabled prior to insertion of any step delay; therefore, the user does not need to account for the Step delay when calculating a suitable WDT time-out value.
  2. Some bits within the PTGCON register are read-only when PTGSTRT = 1 (sequencer executing commands). Refer to PTGCON.