21.4.2.6 Short PWM Code (SPC) Support

The SENT module provides support for implementing SPC with assistance from other external peripherals. The SPCEN (SENTxCON1[6]) bit enables an external Output Compare (OC) peripheral to control the SENT data input pin. In general, a specific OC module is linked in hardware to a specific SENTx module.

To initialize the SENT module for SPC operation:
  1. Set the SPCEN (SENTxCON1[6]) bit to enable control of the SENT data pin by an external source.
  2. For devices with Peripheral Pin Select, map the SENTxTX function to the same I/O pin as SENTxRX.
  3. Configure the Output Compare module as follows:
    1. Configure the module for Triggered mode.
    2. Configure for a single-shot, active-high pulse.
    3. Set the Period and Duty Cycle registers for the desired pulse duration.
After configuration, to use the SPC pulse trigger:
  1. Verify that the line is in a High-Impedance state by polling the RXIDLE bit (SENTxSTAT[1]).
  2. Set the Trigger bit of the OC module to trigger the SPC pulse.

During the active period of the SPC pulse, the SENT receiver edge detection is disabled and the SENT data input pin is driven low by the module. At this time, the receiver logic is reset to prepare for a new data frame. When the pulse is completed, the module releases control of the SENT data input pin and input edge detection is re-enabled, so a data frame can be received from the sensor.

Note: To implement the SPC protocol, the SENT transmitting device(s) must leave the data bus in a High-Impedance state after the falling edge that completes the CRC nibble period. At this time, the SENT data line will be pulled high by the external pull-up resistor. The data bus should not be driven by any transmitter devices until the receiver device requests data by placing a low pulse on the SENT data line.
It is also possible to manually control the SENT data pin to implement the SPC protocol. This can be done as follows:
  1. Clear the ON bit to disable receiver operation.
  2. Manipulate the PORTx and TRISx registers associated with the SENT data pin to drive the data pin low for the desired time.
  3. Return the SENT data pin to a High-Impedance condition using the TRISx register.
  4. Set the ON bit to resume receiver operation.