12.1 Device-Specific Information

Table 12-1. Oscillator Summary
Number of Clock GeneratorsNumber of PLLs
132
Table 12-2. Clock Generator Input and Destination
Clock GeneratorCLKGEN Input Source Module Clock Destination
CLKGEN1All SourcesSystem Clock and Peripheral Clock
CLKGEN2FRC OnlyFRC
CLKGEN3BFRC OnlyBFRC
CLKGEN4All SourcesRAM BIST and NVM BIST
CLKGEN5All SourcesPWM
CLKGEN6All SourcesADC
CLKGEN7All SourcesPDM DAC
CLKGEN8All SourcesUART
CLKGEN9All SourcesSPI
CLKGEN10All SourcesPTG
CLKGEN11All SourcesBiSS
CLKGEN12All SourcesCCP and REFO1
CLKGEN13All SourcesCLC, IOIM and REFO2
Note: CLKGEN 1, 2 and 3 are always ON.
Table 12-3. Clock Generator Input Clock Selections
ValueDescription
1111-1011Reserved
1010 REFI1 – Device REFI1 pin through PPS
1001REFI2 – Device REFI2 pin through PPS
1000PLL2 VCO DIV output
0111PLL1 VCO DIV output
0110PLL2 FOUT output
0101PLL1 FOUT output
0100LPRC as BFRC/244
0011POSC – Primary crystal oscillator (4-32 MHz)
0010BFRC – Internal Backup 8 MHz RC oscillator
0001FRC – Internal 8 MHz RC oscillator
0000ICSP clock (PGC)
Table 12-4. PLL Input Clock Selections
ValueDescription
1111-1011Reserved
1010 REFI1 – Device REFI1 pin through PPS
1001REFI2 – Device REFI2 pin through PPS
1000-0100Reserved
0011POSC – Primary crystal oscillator (4-32 MHz)
0010BFRC – Internal Backup 8 MHz RC oscillator
0001FRC – Internal 8 MHz RC oscillator
0000ICSP clock (PGC)
Table 12-5. Clock Monitor CNTSEL/WINSEL Input Clock Selections
ValueDescription
0x11010REFI2 - Device REFI1 pin through PPS
0x11001REFI1 - Device REFI2 pin through PPS
0x11000-0x10101Reserved
0x10100BRFC/244
0x10011POSC - Primary crystal oscillator (4-32 MHz)
0x10010BFRC - Internal Backup 8 MHz RC oscillator
0x10001FRC - Internal 8 MHz RC oscillator
0x10000ISCP clock (PGC)
0x01111Reserved
0x01110PLL2 VCO DIV output
0x01101PLL2 FOUT output
0x01100PLL1 VCO DIV output
0x01011PLL1 FOUT output
0x01010 CLKGEN11
0x01001CLKGEN10
0x01000CLKGEN9
0x00111CLKGEN8
0x00110CLKGEN7
0x00101CLKGEN6
0x00100CLKGEN5
0x00011CLKGEN4
0x00010CLKGEN3
0x00001CLKGEN2
0x00000CLKGEN1
Note: Refer to Table 37-25 for minimum and maximum peripheral clock frequencies.