5.4.6 Error Correcting Code (ECC)

To improve data memory performance and reliability, the dsPIC33AK128MC106 device family includes Error Correcting Code (ECC) functionality as an integral part of the data memory. ECC can determine the presence of single-bit errors in data memory, including which bit is in error, and correct the data without user intervention. Both X and Y memory support ECC and have their own control registers.

Each 32-bit data word in SRAM is completed by seven additional ECC bits, which are not accessible by the user.

Upon any 8/16/32-bit write in the memory, the seven ECC bits are computed and stored along with the data (the 8/16-bits writes are actually composed of an atomic read of 32 bits, modify, and write of 32 bits).

Upon any 8/16/32-bit read in the memory, if the ECC feature is disabled, then single or double errors are not detected and are not corrected. If the ECC feature is enabled, the ECC syndrome is computed on the related 32 data bits + 7 ECC bits.

Single-bit errors are automatically identified and corrected on read back. An interrupt is generated if enabled. Double-bit errors will be identified but not corrected. Either bus error or generic error traps are generated based on read or write path double-bit errors.

ECC operations for partial 8/16-bit write/read to data memory utilize PWB registers.

ECC operations for full word 32-bit write/read to data utilize RAM registers.

The user controls the ECC Fault injection through the ECCCON, ECCFPTR, ECCFADDR and ECCSTAT SFRs. Users may either create intentional Faults in data read from the data RAM, or in data written into the data RAM. To report ECC Faults, the ECCFADDR must be configured with the target data memory location and subsequently read. Single or double-bit Faults may be injected into any location within the data word (i.e., any data bit including the ECC parity bits).