6.3.3 Flash ECC

To improve program memory performance and durability, select dsPIC33A devices include ECC functionality as an integral part of the Flash memory controller. ECC can determine the presence of single-bit errors in program data, including which bit is in error, and correct the data without user intervention. When implemented, ECC is automatic and cannot be disabled.

Additionally, users can inject single-bit errors or double-bit errors into the ECC calculation. This allows functional safety focused users to be able to test the ECC calculation and Fault generation logic at run time to verify there are no latent Faults present in the system.

When data is written to program memory, ECC generates a 9-bit Hamming code parity value, 8-bit Single Error Correction (SEC) value and one extra bit to support Double Error Correction (DED) for every 128-bit input data value. Parity data is not memory-mapped and is inaccessible. When the data is read back, the ECC calculates parity on it and compares it to the previously stored parity value. If a parity mismatch occurs, there are two possible outcomes:

  • Single-bit errors are automatically identified and corrected on read back. An optional device-level interrupt is also generated.
    Note: The single-bit interrupt vector is called NVMECCInterrupt, and NVMECCIF is the associated flag.
  • Double-bit errors will generate a soft trap. If special exception handling for the trap is not implemented, a device Reset will also occur.
    Note: A bus error trap will be generated for an ECC double-bit error, and INTCON3.XRAMBET is the associated flag.

The user controls the ECC Fault injection through the ECCCON, ECCFPTR, ECCFADDR and the ECCSTAT SFRs. In keeping with all other NVM Controller SFRs, writes to these registers are inhibited during any Flash write sequence. Users may either create intentional Faults in data read from the Flash or in data written into the Flash. Single-bit or double-bit Faults may be injected into any location within the data word (i.e., any data bit but also including the ECC parity bits).