27.2.3 CRC Data Register

Table 27-3. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	CRCDAT
Offset:	0x2D0


Bit	31	30	29	28	27	26	25	24
	DATA[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset


Bit	23	22	21	20	19	18	17	16
	DATA[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset


Bit	15	14	13	12	11	10	9	8
	DATA[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset


Bit	7	6	5	4	3	2	1	0
	DATA[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset

Bits 31:0 – DATA[31:0] CRC Input Data bits

Writing to this register fills the FIFO. Reading from this register returns ‘0’

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