30.8.4 CLCnSEL0

Generic CLCn Data 1 Select Register
Name: CLCnSEL0
Offset: 0x068E

Bit 76543210 
  D1S[6:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset xxxxxxx 

Bits 6:0 – D1S[6:0] CLCn Data1 Input Selection

Table 30-2. CLC Input Selection
DyS Input Source DyS (cont.) Input Source (cont.)
[0] 0000 0000 CLCIN0PPS [32] 0010 0000 C2_OUT
[1] 0000 0001 CLCIN1PPS [33] 0010 0001 ZCD_OUT
[2] 0000 0010 CLCIN2PPS [34] 0010 0010 IOCIF
[3] 0000 0011 CLCIN3PPS [35] 0010 0011 CLC1_OUT
[4] 0000 0100 FOSC [36] 0010 0100 CLC2_OUT
[5] 0000 0101 HFINTOSC [37] 0010 0101 CLC3_OUT
[6] 0000 0110 LFINTOSC [38] 0010 0110 CLC4_OUT
[7] 0000 0111 MFINTOSC (500 kHz) [39] 0010 0111 TX1/CK1
[8] 0000 1000 MFINTOSC (32 kHz) [40] 0010 1000 TX2/CK2
[9] 0000 1001 — [41] 0010 1001 SDA1/SDO1
[10] 0000 1010 SOSC [42] 0010 1010 SCL1/SCK1
[11] 0000 1011 EXTOSC [43] 0010 1011 SDA2/SDO2
[12] 0000 1100 ADCRC [44] 0010 1100 SCL2/SCK2
[13] 0000 1101 CLKR_OUT [45] 0010 1101 CWG1A_OUT
[14] 0000 1110 TMR0_Overflow [46] 0010 1110 CWG1B_OUT
[15] 0000 1111 TMR1_Overflow ... —
[16] 0001 0000 TMR2_Postscaled_OUT ... —
[17] 0001 0001 TMR3_Overflow ... —
[18] 0001 0010 TMR4_Postscaled_OUT ... —
[19] 0001 0011 — ... —
[20] 0001 0100 CCP1_OUT ... —
[21] 0001 0101 CCP2_OUT ... —
[22] 0001 0110 PWM1S1P1_OUT ... —
[23] 0001 0111 PWM1S1P2_OUT ... —
[24] 0001 1000 PWM2S1P1_OUT ... —
[25] 0001 1001 PWM2S1P2_OUT ... —
[26] 0001 1010 — ... —
[27] 0001 1011 — ... —
[28] 0001 1100 — ... —
[29] 0001 1101 — ... —
[30] 0001 1110 NCO1_OUT ... —
[31] 0001 1111 C1_OUT [127] 0111 1111 —
Reset States: 
POR/BOR = xxxxxxx
All Other Resets = uuuuuuu