PIC32CX SG41/SG60/SG61 Family Data Sheet

25.6.18 Channel Priority Level

Name:	CHPRILVL
Offset:	0x45 + n*0x10 [n=0..31]
Reset:	0x00
Property:	PAC Write-Protection


Bit	7	6	5	4	3	2	1	0
							PRILVL[1:0]
Access							R/W	R/W
Reset							0	0

Bits 1:0 – PRILVL[1:0] Channel Priority Level

These bits define the priority level used for the DMA channel. The available levels are shown below, where a high level has priority over a low level. These bits are not enable-protected.

Value	Name	Description
0x0	LVL0	Channel Priority Level 0 (Lowest Level)
0x1	LVL1	Channel Priority Level 1
0x2	LVL2	Channel Priority Level 2
0x3	LVL3	Channel Priority Level 3 (Highest Level)

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