25.6.16 Channel Control A
Name: | CHCTRLA |
Offset: | 0x40 + n*0x10 [n=0..31] |
Reset: | 0x00000000 |
Property: | PAC Write-Protection, Enable-Protected |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
THRESHOLD[1:0] | BURSTLEN[3:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
TRIGACT[1:0] | |||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
TRIGSRC[6:0] | |||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
RUNSTDBY | ENABLE | SWRST | |||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 0 | 0 |
Bits 29:28 – THRESHOLD[1:0] FIFO Threshold
These bits are not enable-protected.
Value | Name | Description |
---|---|---|
0x0 | 1BEAT | Destination write starts after each beat source addess read |
0x1 | 2BEATS | Destination write starts after 2-beats source address read |
0x2 | 4BEATS | Destination write starts after 4-beats source address read |
0x3 | 8BEATS | Destination write starts after 8-beats source address read |
Bits 27:24 – BURSTLEN[3:0] Burst Length
These bits are not enable-protected.
Value | Name | Description |
---|---|---|
0x0 | SINGLE | Single-beat burst |
0x1 | 2BEAT | 2-beats burst length |
0x2 | 3BEAT | 3-beats burst length |
0x3 | 4BEAT | 4-beats burst length |
0x4 | 5BEAT | 5-beats burst length |
0x5 | 6BEAT | 6-beats burst length |
0x6 | 7BEAT | 7-beats burst length |
0x7 | 8BEAT | 8-beats burst length |
0x8 | 9BEAT | 9-beats burst length |
0x9 | 10BEAT | 10-beats burst length |
0xA | 11BEAT | 11-beats burst length |
0xB | 12BEAT | 12-beats burst length |
0xC | 13BEAT | 13-beats burst length |
0xD | 14BEAT | 14-beats burst length |
0xE | 15BEAT | 15-beats burst length |
0xF | 16BEAT | 16-beats burst length |
Bits 21:20 – TRIGACT[1:0] Trigger Action
These bits are not enable-protected.
Value | Name | Description |
---|---|---|
0x0 | BLOCK | One trigger required for each block transfer |
0x1 | Reserved | |
0x2 | BURST | One trigger required for each burst transfer |
0x3 | TRANSACTION | One trigger required for each transaction |
Bits 14:8 – TRIGSRC[6:0] Trigger Source
Index | Instance | Channel | Presentation |
---|---|---|---|
0x00 | DISABLE | Only software/event triggers | |
0x01 | RTC | TIMESTAMP | DMA RTC timestamp trigger |
0x02 | DSU | DCC0 | DMAC ID for DCC0 register |
0x03 | DSU | DCC1 | DMAC ID for DCC1 register |
0x04 | SERCOM0 | RX | Index of DMA RX trigger |
0x05 | SERCOM0 | TX | Index of DMA TX trigger |
0x06 | SERCOM1 | RX | Index of DMA RX trigger |
0x07 | SERCOM1 | TX | Index of DMA TX trigger |
0x08 | SERCOM2 | RX | Index of DMA RX trigger |
0x09 | SERCOM2 | TX | Index of DMA TX trigger |
0x0A | SERCOM3 | RX | Index of DMA RX trigger |
0x0B | SERCOM3 | TX | Index of DMA TX trigger |
0x0C | SERCOM4 | RX | Index of DMA RX trigger |
0x0D | SERCOM4 | TX | Index of DMA TX trigger |
0x0E | SERCOM5 | RX | Index of DMA RX trigger |
0x0F | SERCOM5 | TX | Index of DMA TX trigger |
0x10 | SERCOM6 | RX | Index of DMA RX trigger |
0x11 | SERCOM6 | TX | Index of DMA TX trigger |
0x12 | SERCOM7 | RX | Index of DMA RX trigger |
0x13 | SERCOM7 | TX | Index of DMA TX trigger |
0x14 | CAN0 | DEBUG | DMA CAN Debug Req |
0x15 | CAN1 | DEBUG | DMA CAN Debug Req |
0x16 | TCC0 | OVF | DMA overflow/underflow/retrigger trigger |
0x1C - 0x17 | TCC0 | MC | Indexes of DMA Match/Compare triggers |
0x1D | TCC1 | OVF | DMA overflow/underflow/retrigger trigger |
0x21- 0x1E | TCC1 | MC | Indexes of DMA Match/Compare triggers |
0x22 | TCC2 | OVF | DMA overflow/underflow/retrigger trigger |
0x25 - 0x23 | TCC2 | MC | Indexes of DMA Match/Compare triggers |
0x26 | TCC3 | OVF | DMA overflow/underflow/retrigger trigger |
0x28 - 0x27 | TCC3 | MC | Indexes of DMA Match/Compare triggers |
0x29 | TCC4 | OVF | DMA overflow/underflow/retrigger trigger |
0x2B - 0x2A | TCC4 | MC | Indexes of DMA Match/Compare triggers |
0x2C | TC0 | OVF | Indexes of DMA Overflow trigger |
0x2E - 0x2D | TC0 | MC | Indexes of DMA Match/Compare triggers |
0x2F | TC1 | OVF | Indexes of DMA Overflow trigger |
0x31 - 0x30 | TC1 | MC | Indexes of DMA Match/Compare triggers |
0x32 | TC2 | OVF | Indexes of DMA Overflow trigger |
0x34 - 0x33 | TC2 | MC | Indexes of DMA Match/Compare triggers |
0x35 | TC3 | OVF | Indexes of DMA Overflow trigger |
0x37 - 0x36 | TC3 | MC | Indexes of DMA Match/Compare triggers |
0x38 | TC4 | OVF | Indexes of DMA Overflow trigger |
0x3A - 0x39 | TC4 | MC | Indexes of DMA Match/Compare triggers |
0x3B | TC5 | OVF | Indexes of DMA Overflow trigger |
0x3D:0x3C | TC5 | MC | Indexes of DMA Match/Compare triggers |
0x3E | TC6 | OVF | Indexes of DMA Overflow trigger |
0x40 - 0x3F | TC6 | MC | Indexes of DMA Match/Compare triggers |
0x41 | TC7 | OVF | Indexes of DMA Overflow trigger |
0x43 - 0x41 | TC7 | MC | Indexes of DMA Match/Compare triggers |
0x44 | ADC0 | RESRDY | index of DMA RESRDY trigger |
0x45 | ADC0 | SEQ | Index of DMA SEQ trigger |
0x46 | ADC1 | RESRDY | Index of DMA RESRDY trigger |
0x47 | ADC1 | SEQ | Index of DMA SEQ trigger |
0x49 - 0x48 | DAC | EMPTY | DMA DAC Empty Req |
0x4B - 0x4A | DAC | RESRDY | DMA DAC Result Ready Req |
0x4D - 0x4C | I2S | RX | Indexes of DMA RX triggers |
0x4F - 0x4E | I2S | TX | Indexes of DMA TX triggers |
0x50 | PCC | RX | Indexes of PCC RX trigger |
0x51 | AES | WR | DMA DATA Write trigger |
0x52 | AES | RD | DMA DATA Read trigger |
0x53 | QSPI | RX | Indexes of QSPI RX trigger |
0x54 | QSPI | TX | Indexes of QSPI TX trigger |
Bit 6 – RUNSTDBY Channel run in standby
This bit is used to keep the DMAC channel running in standby mode.
This bit is not enable-protected.
Value | Description |
---|---|
0 | The DMAC channel is halted in standby. |
1 | The DMAC channel continues to run in standby. |
Bit 1 – ENABLE Channel Enable
Writing a '0' to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst transfer is completed.
Writing a '1' to this bit will enable the DMA channel.
This bit is not enable-protected.
Value | Description |
---|---|
0 | DMA channel is disabled. |
1 | DMA channel is enabled. |
Bit 0 – SWRST Channel Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets the channel registers to their initial state. The bit can be set when the channel is disabled (ENABLE=0). Writing a '1' to this bit will be ignored as long as ENABLE=1. This bit is automatically cleared when the reset is completed.
Value | Description |
---|---|
0 | There is no reset operation ongoing. |
1 | The reset operation is ongoing. |