25.6.2 CRC Control

Name:	CRCCTRL
Offset:	0x02
Reset:	0x0000
Property:	PAC Write-Protection, Enable-Protected


Bit	15	14	13	12	11	10	9	8
	CRCMODE[1:0]		CRCSRC[5:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
					CRCPOLY[1:0]		CRCBEATSIZE[1:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 15:14 – CRCMODE[1:0] CRC Operating Mode

These bits define the block transfer mode.

Value	Name	Description
0x0	DEFAULT	Default operating mode
0x1	-	Reserved
0x2	CRCMON	Memory CRC monitor operating mode
0x3	CRCGEN	Memory CRC generation operating mode

Bits 13:8 – CRCSRC[5:0] CRC Input Source

These bits select the input source for generating the CRC. The selected source is locked until either the CRC generation is completed or the CRC module is disabled. This means the CRCSRC cannot be modified when the CRC operation is ongoing. The lock is signaled by the CRCBUSY status bit. The CRC generation complete is generated and signaled from the selected source when used with the DMA Channel.

Value	Name	Description
0x00	DISABLE	No action
0x01	IO	I/O interface
0x02 - 0x1F	-	Reserved
0x20	CHN0	DMA Channel 0
0x21	CHN1	DMA Channel 1
0x22	CHN2	DMA Channel 2
0x23	CHN3	DMA Channel 3
0x24	CHN4	DMA Channel 4
0x25	CHN5	DMA Channel 5
0x26	CHN6	DMA Channel 6
0x27	CHN7	DMA Channel 7
0x28	CHN8	DMA Channel 8
0x29	CHN9	DMA Channel 9
0x2A	CHN10	DMA Channel 10
0x2B	CHN11	DMA Channel 11
0x2C	CHN12	DMA Channel 12
0x2D	CHN13	DMA Channel 13
0x2E	CHN14	DMA Channel 14
0x2F	CHN15	DMA Channel 15
0x30	CHN16	DMA Channel 16
0x31	CHN17	DMA Channel 17
0x32	CHN18	DMA Channel 18
0x33	CHN19	DMA Channel 19
0x34	CHN20	DMA Channel 20
0x35	CHN21	DMA Channel 21
0x36	CHN22	DMA Channel 22
0x37	CHN23	DMA Channel 23
0x38	CHN24	DMA Channel 24
0x39	CHN25	DMA Channel 25
0x3A	CHN26	DMA Channel 26
0x3B	CHN27	DMA Channel 27
0x3C	CHN28	DMA Channel 28
0x3D	CHN29	DMA Channel 29
0x3E	CHN30	DMA Channel 30
0x3F	CHN31	DMA Channel 31