45.7.1 Control A

Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized Bits, Enable-Protected

Bit 3130292827262524 
   CPTEN5CPTEN4CPTEN3CPTEN2CPTEN1CPTEN0 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 2322212019181716 
 DMAOS        
Access R/W 
Reset 0 
Bit 15141312111098 
 MSYNCALOCKPRESCSYNC[1:0]RUNSTDBYPRESCALER[2:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
  RESOLUTION[1:0]   ENABLESWRST 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 24, 25, 26, 27, 28, 29 – CPTENx Capture Channel x Enable, x = 0..5

These bits are used to select the capture or compare operation on channel x.

Writing a '1' to CPTENx enables capture on channel x.

Writing a '0' to CPTENx disables capture on channel x.

Bit 23 – DMAOS DMA One-Shot Trigger Mode

This bit enables the DMA One-shot Trigger Mode.

Writing a '1' to this bit will generate a DMA trigger on TCC cycle following a TCC_CTRLBSET_CMD_DMAOS command.

Writing a '0' to this bit will generate DMA triggers on each TCC cycle.

This bit is not synchronized.

Bit 15 – MSYNC Host Synchronization (only for TCC Client instance)

This bit must be set if the TCC counting operation must be synchronized on its Host TCC.

This bit is not synchronized.

ValueDescription
0 The TCC controls its own counter.
1 The counter is controlled by its Host TCC.

Bit 14 – ALOCK Auto Lock

This bit is not synchronized.

ValueDescription
0 The Lock Update bit in the Control B register (CTRLB.LUPD) is not affected by overflow/underflow, and re-trigger events
1 CTRLB.LUPD is set to '1' on each overflow/underflow or re-trigger event.

Bits 13:12 – PRESCSYNC[1:0] Prescaler and Counter Synchronization

These bits select if on re-trigger event, the Counter is cleared or reloaded on either the next GCLK_TCCx clock, or on the next prescaled GCLK_TCCx clock. It is also possible to reset the prescaler on re-trigger event.

These bits are not synchronized.

Value Name Description
Counter Reloaded Prescaler
0x0 GCLK Reload or reset Counter on next GCLK -
0x1 PRESC Reload or reset Counter on next prescaler clock -
0x2 RESYNC Reload or reset Counter on next GCLK Reset prescaler counter
0x3 Reserved

Bit 11 – RUNSTDBY Run in Standby

This bit is used to keep the TCC running in Standby mode.

This bit is not synchronized.

ValueDescription
0 The TCC is halted in standby.
1 The TCC continues to run in standby.

Bits 10:8 – PRESCALER[2:0] Prescaler

These bits select the Counter prescaler factor.

These bits are not synchronized.

ValueNameDescription
0x0 DIV1 Prescaler: GCLK_TCCx
0x1 DIV2 Prescaler: GCLK_TCCx/2
0x2 DIV4 Prescaler: GCLK_TCCx/4
0x3 DIV8 Prescaler: GCLK_TCCx/8
0x4 DIV16 Prescaler: GCLK_TCCx/16
0x5 DIV64 Prescaler: GCLK_TCCx/64
0x6 DIV256 Prescaler: GCLK_TCCx/256
0x7 DIV1024 Prescaler: GCLK_TCCx/1024

Bits 6:5 – RESOLUTION[1:0] Dithering Resolution

These bits increase the TCC resolution by enabling the dithering options.

These bits are not synchronized.

Table 45-8. Dithering
Value Name Description
0x0 NONE The dithering is disabled.
0x1 DITH4 Dithering is done every 16 PWM frames.

PER[3:0] and CCx[3:0] contain dithering pattern selection.

0x2 DITH5 Dithering is done every 32 PWM frames.

PER[4:0] and CCx[4:0] contain dithering pattern selection.

0x3 DITH6 Dithering is done every 64 PWM frames.

PER[5:0] and CCx[5:0] contain dithering pattern selection.

Bit 1 – ENABLE Enable

Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the ENABLE bit in the SYNCBUSY register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.

ValueDescription
0 The peripheral is disabled.
1 The peripheral is enabled.

Bit 0 – SWRST Software Reset

Writing a '0' to this bit has no effect.

Writing a '1' to this bit resets all registers in the TCC (except DBGCTRL) to their initial state, and the TCC will be disabled.

Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be discarded.

Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.

Note:
  1. When the CTRLA.SWRST is written, the user must poll the SYNCBUSY.SWRST bit to know when the reset operation is complete.
  2. During a SWRST, access to registers/bits without the SWRST are disallowed until the SYNCBUSY.SWRST is cleared by hardware.
ValueDescription
0 There is no Reset operation ongoing.
1 The Reset operation is ongoing.