45.7.20 Period Buffer Value
Note: This register is write-synchronized: SYNCBUSY.PER must be checked to ensure the PER
register synchronization is complete.
| Name: | PERBUF |
| Offset: | 0x6C |
| Reset: | 0xFFFFFFFF |
| Property: | Write-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PERBUF[17:10] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PERBUF[9:2] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PERBUF[1:0] | DITHERBUF[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bits 23:6 – PERBUF[17:0] Period Buffer Value
These bits hold the value of the Period Buffer register. The value is copied to PER register on UPDATE condition.
Note: When the TCC is configured as
16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of
the register, [23:m]. m is dependent on the Resolution bit in the Control A register
(CTRLA.RESOLUTION):
| CTRLA.RESOLUTION | Bits [23:m] |
|---|---|
| 0x0 - NONE | 23:0 |
| 0x1 - DITH4 | 23:4 |
| 0x2 - DITH5 | 23:5 |
| 0x3 - DITH6 | 23:6 (depicted) |
Bits 5:0 – DITHERBUF[5:0] Dithering Buffer Cycle Number
Note: This bit field consists of the n LSB
of the register. n is dependent on the value of the Resolution bits in the Control A
register (CTRLA.RESOLUTION):
| CTRLA.RESOLUTION | Bits [n:0] |
|---|---|
| 0x0 - NONE | - |
| 0x1 - DITH4 | 3:0 |
| 0x2 - DITH5 | 4:0 |
| 0x3 - DITH6 | 5:0 (depicted) |