13.12.9 Configuration

Name: CFG
Offset: 0x1C
Reset: 0x00000002
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
    ETBRAMENDCCDMALEVEL[1:0]LQOS[1:0] 
Access R/WR/WR/WR/WR/W 
Reset 00010 

Bit 4 – ETBRAMEN Trace Control

ETB Ram Enable Writing a one to this bit will reserve the first 32KB of the RAM for the Trace ETB ram buffer. Refer to Memories / SRAM Memory Configuration section for details.

Bits 3:2 – DCCDMALEVEL[1:0] DMA Trigger Level

ValueDescription
0x0 DMA Trigger rises when DCC is empty.
0x1 DMA Trigger rises when DCC is full.
0x2 - 0x3 Reserved

Bits 1:0 – LQOS[1:0] Latency Quality Of Service

These bits define the priority access during the memory access. Refer to SRAM Quality of Service.