27.5.11 Line Cache

NVM reads 128-bit at a time. The AHB0 and AHB1 interfaces implement each a 128-bit cache line. This reduces the device power consumption when reading continuous data and improves system performance when wait states are required. Line cache are enabled by default and can be individually disabled per AHB interface by writing a one in the CACHEDIS[0] or CACHEDIS[1] bit in the CTRLA register (CTRLA.CACHEDIS[1:0]). Refer to the CTRLA register description for additional information. Commands affecting NVM content automatically invalidate cache lines.