4.4.3.1.1.2 CHCR – Channel
Filter Configuration Register
This register must be
modified only if the channel filter is disabled (RDPR.PRFLT = 1). Modifying the settings
during operation may lead to unstable operation.| Name: | CHCR |
| Offset: | 0x0A9 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | BWM[3:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – Reserved
Bit
Reserved for future use, read
as ‘0’.
Bit 6 – Reserved Bit
Reserved for future use, read
as ‘0’.
Bit 5 – Reserved Bit
Reserved for future use, read
as ‘0’.
Bit 4 – Reserved Bit
Reserved for future use, read
as ‘0’.
Bits 3:0 – BWM[3:0] Bandwidth
mode
Adapts the filter frequency
transfer function to the application. For more details about the required setting
for each supported bandwidth, see Filter Settings for Each Supported
Bandwidth in the Channel Filter from Related
Links.
