37.5.9 I2CxCLK

I2C Clock Selection Register

Name:	I2CxCLK
Offset:	0x029E


Bit	7	6	5	4	3	2	1	0
				CLK[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – CLK[4:0] I2C Clock Selection

Table 37-4.
CLK	Selection
`11000-11111`	Reserved
`10111`	CLC8_out
`10110`	CLC7_out
`10101`	CLC6_out
`10100`	CLC5_out
`10011`	CLC4_out
`10010`	CLC3_out
`10001`	CLC2_out
`10000`	CLC1_out
`01111`	SMT1 overflow
`01100-01110`	Reserved
`01011`	TU16B_out
`01010`	TU16A_out
`01001`	TMR6 post scaled output
`01000`	TMR4 post scaled output
`00111`	TMR2 post scaled output
`00110`	TMR0 overflow
`00101`	EXTOSC
`00100`	Clock Reference output
`00011`	MFINTOSC (500 kHz)
`00010`	HFINTOSC
`00001`	F_OSC
`00000`	F_OSC/4

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