16.8 DMA Setup and Operation

The following steps illustrate how to configure the DMA for data transfer:

  1. Select the desired DMA using the DMASELECT register.
  2. Program the appropriate source and destination addresses for the transaction into the DMAnSSA and DMAnDSA registers.
  3. Select the source memory region that is being addressed by the DMAnSSA register, using the SMR bits.
  4. Program the SMODE and DMODE bits to select the Addressing mode.
  5. Program the source size (DMAnSSZ) and destination size (DMAnDSZ) registers with the number of bytes to be transferred. It is recommended for proper operation that the size registers be a multiple of each other.
  6. If the user desires to disable data transfers once the message has completed, then the SSTP and DSTP bits need to be set (see the Source/Destination Stop section).
  7. If using hardware triggers for data transfer, set up the hardware trigger interrupt sources for the starting and aborting DMA transfers (DMAnSIRQ and DMAnAIRQ), and set the corresponding Interrupt Request Enable (SIRQEN and AIRQEN) bits.
  8. Select the priority level for the DMA (see the “System Arbitration” section in the “PIC18 CPU” chapter) and lock the priorities (see the “Priority Lock” section in the “PIC18 CPU” chapter).
  9. Enable the DMA by setting the EN bit.
  10. If using software control for data transfer, set the DGO bit, else this bit will be set by the hardware trigger.

Once the DMA is set up, Figure 16-5 describes the sequence of operation when the DMA uses hardware triggers and utilizes the unused CPU cycles (bubble) for DMA transfers.

The following sections describe with visual reference the sequence of events for different configurations of the DMA module.

Figure 16-5. DMA Operation with Hardware Trigger