Jump to main content

28/40/44/48-Pin, Low-Power, High-Performance Microcontroller with XLP Technology

PIC18F27Q83 PIC18F47Q83 PIC18F57Q83

Home
14 Resets
14.3 Low-Power Brown-out Reset (LPBOR)
14.3.1 Enabling LPBOR

Introduction
PIC18-Q83 Family Types
Features
1 Packages
2 Pin Diagrams
3 Pin Allocation Tables
4 Guidelines for Getting Started with PIC18-Q83 Microcontrollers
5 Register and Bit Naming Conventions
6 Register Legend
7 PIC18 CPU
8 Device Configuration
9 Memory Organization
10 NVM - Nonvolatile Memory Module
11 VIC - Vectored Interrupt Controller Module
12 OSC - Oscillator Module (With Fail-Safe Clock Monitor)
13 CRC - Cyclic Redundancy Check Module with Memory Scanner
14 Resets
15 WWDT - Windowed Watchdog Timer
16 DMA - Direct Memory Access
17 Power-Saving Modes
18 PMD - Peripheral Module Disable
19 I/O Ports
20 IOC - Interrupt-on-Change
21 PPS - Peripheral Pin Select Module
22 CLC - Configurable Logic Cell
23 CLKREF - Reference Clock Output Module
24 TMR0 - Timer0 Module
25 TMR1 - Timer1 Module with Gate Control
26 TMR2 - Timer2 Module
27 SMT - Signal Measurement Timer
28 UTMR - Universal Timer Module
29 CCP - Capture/Compare/PWM Module
30 Capture, Compare, and PWM Timers Selection
31 PWM - Pulse-Width Modulator with Compare
32 CWG - Complementary Waveform Generator Module
33 NCO - Numerically Controlled Oscillator Module
34 DSM - Data Signal Modulator Module
35 UART - Universal Asynchronous Receiver Transmitter with Protocol Support
36 SPI - Serial Peripheral Interface Module
37 I²C - Inter-Integrated Circuit Module
38 CAN - Controller Area Network
39 JTAG Boundary Scan
40 HLVD - High/Low-Voltage Detect
41 FVR - Fixed Voltage Reference
42 Temperature Indicator Module
43 ADC - Analog-to-Digital Converter with Computation and Context Module
44 DAC - Digital-to-Analog Converter Module - 8-Bit
45 CMP - Comparator Module
46 ZCD - Zero-Cross Detection Module
47 Instruction Set Summary
48 ICSP™ - In-Circuit Serial Programming™
49 Register Summary
50 Electrical Specifications
51 DC and AC Characteristics Graphs and Tables
52 Packaging Information
53 Appendix A: Revision History
Microchip Information

14.3.1 Enabling LPBOR

The LPBOR is controlled by the LPBOREN Configuration bit. When the device is erased, the LPBOR module defaults to disabled.

About

Company

Careers

Contact Us

Media Center

Investor Relations

Corporate Responsibility

Support

Microchip Forums

AVR Freaks

Design Help

Technical Support

Export Control Data

PCNs

Quick Links

microchipDIRECT.com

Microchip University

myMicrochip

Blogs

Reference Designs

Parametric Search

Microchip Technology Inc.

2355 West Chandler Blvd.

Chandler, Arizona, USA

Microchip Twitter

Microchip Weibo

© Copyright 1998-2024 Microchip Technology Inc. All rights reserved. Shanghai ICP Recordal No.09049794

Terms Of Use

Privacy Notice

Legal

Your Privacy Choices California Consumer Privacy Act (CCPA) Opt-Out Icon

California Consumer Privacy Act (CCPA) Opt-Out Icon