18.9.1 TC0 Control Register A
| Name: | TCCR0A |
| Offset: | 0x44 |
| Reset: | 0x00 |
| Property: | When addressing as I/O register: address offset is 0x24 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| COM0A[1:0] | COM0B [1:0] | WGM0[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 7:6 – COM0A[1:0] Compare Output Mode for Channel A
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A[1:0] bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A[1:0] bits depends on the WGM0[2:0] bit setting. The table below shows the COM0A[1:0] bit functionality when the WGM0[2:0] bits are set to a normal or CTC mode (non-PWM).
| COM0A[1] | COM0A[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC0A disconnected. |
| 0 | 1 | Toggle OC0A on compare match. |
| 1 | 0 | Clear OC0A on compare match. |
| 1 | 1 | Set OC0A on compare match. |
The table below shows the COM0A[1:0] bit functionality when the WGM0[1:0] bits are set to fast PWM mode.
| COM0A[1] | COM0A[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC0A disconnected. |
| 0 | 1 |
WGM0[2:0]: Normal port operation, OC0A disconnected. WGM0[2:1]: Toggle OC0A on compare match. |
| 1 | 0 | Clear OC0A on compare match, set OC0A at BOTTOM (Non-inverting mode). |
| 1 | 1 | Set OC0A on compare match, clear OC0A at BOTTOM (Inverting mode). |
- A special case occurs when OCR0A equals TOP and COM0A[1] is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. Refer to Fast PWM Mode for details.
The table below shows the COM0A[1:0] bit functionality when the WGM0[2:0] bits are set to phase correct PWM mode.
| COM0A[1] | COM0A[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC0A disconnected. |
| 0 | 1 |
WGM0[2:0]: Normal port operation, OC0A disconnected. WGM0[2:1]: Toggle OC0A on compare match. |
| 1 | 0 | Clear OC0A on compare match when up-counting. Set OC0A on compare match when down-counting. |
| 1 | 1 | Set OC0A on compare match when up-counting. Clear OC0A on compare match when down-counting. |
- A special case occurs when OCR0A equals TOP and COM0A[1] is set. In this case, the compare match is ignored, but the set or clear is done at TOP. Refer to Phase Correct PWM Mode for details.
Bits 5:4 – COM0B [1:0] Compare Output Mode for Channel B
These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B[1:0] bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to enable the output driver.
When OC0B is connected to the pin, the function of the COM0B[1:0] bits depends on the WGM0[2:0] bit setting. The table shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to a normal or CTC mode (non- PWM).
| COM0B[1] | COM0B[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC0B disconnected. |
| 0 | 1 | Toggle OC0B on compare match. |
| 1 | 0 | Clear OC0B on compare match. |
| 1 | 1 | Set OC0B on compare match. |
The table below shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to fast PWM mode.
| COM0B[1] | COM0B[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC0B disconnected. |
| 0 | 1 | Reserved. |
| 1 | 0 | Clear OC0B on compare match, set OC0B at BOTTOM, (Non-inverting mode). |
| 1 | 1 | Set OC0B on compare match, clear OC0B at BOTTOM, (Inverting mode). |
- A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. Refer to Fast PWM Mode for details.
The table below shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to phase correct PWM mode.
| COM0B[1] | COM0B[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC0B disconnected. |
| 0 | 1 | Reserved. |
| 1 | 0 | Clear OC0B on compare match when up-counting. Set OC0B on compare match when down-counting. |
| 1 | 1 | Set OC0B on compare match when up-counting. Clear OC0B on compare match when down-counting. |
- A special case occurs when OCR0B equals TOP and COM0B[1] is set. In this case, the compare match is ignored, but the set or clear is done at TOP. Refer to Phase Correct PWM Mode for details.
Bits 1:0 – WGM0[1:0] Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see Modes of Operation).
| Mode | WGM0[2] | WGM0[1] | WGM0[0] | Timer/Counter Mode of Operation | TOP | Update of OCR0x at | TOV Flag Set on(1)(2) |
|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | Normal | 0xFF | Immediate | MAX |
| 1 | 0 | 0 | 1 | PWM, Phase Correct | 0xFF | TOP | BOTTOM |
| 2 | 0 | 1 | 0 | CTC | OCR0A | Immediate | MAX |
| 3 | 0 | 1 | 1 | Fast PWM | 0xFF | BOTTOM | MAX |
| 4 | 1 | 0 | 0 | Reserved | - | - | - |
| 5 | 1 | 0 | 1 | PWM, Phase Correct | OCR0A | TOP | BOTTOM |
| 6 | 1 | 1 | 0 | Reserved | - | - | - |
| 7 | 1 | 1 | 1 | Fast PWM | OCR0A | BOTTOM | TOP |
- MAX = 0xFF
- BOTTOM = 0x00