Bit 2 – OCIE0B Timer/Counter0,
Output Compare B Match Interrupt Enable
When the OCIE0B bit
is written to one, and the I-bit in the Status register is set, the Timer/Counter
compare match B interrupt is enabled. The corresponding interrupt is executed if a
compare match in Timer/Counter occurs, i.e., when the OCF0B bit is set in TIFR0.
Bit 1 – OCIE0A Timer/Counter0,
Output Compare A Match Interrupt Enable
When the OCIE0A bit
is written to one, and the I-bit in the Status register is set, the Timer/Counter0
Compare Match A interrupt is enabled. The corresponding interrupt is executed if a
compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in TIFR0.
Bit 0 – TOIE0 Timer/Counter0,
Overflow Interrupt Enable
When the TOIE0 bit
is written to one, and the I-bit in the Status register is set, the Timer/Counter0
overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in TIFR0.
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