19.6 Input Capture Unit

The Timer/Countern incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICPn pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively, the time-stamps can be used for creating a log of the events.

The input capture unit is illustrated by the block diagram below. The elements of the block diagram that are not directly a part of the input capture unit are gray shaded. The lower case “n” in register and bit names indicates the Timer/Counter number.

Figure 19-2. Input Capture Unit Block Diagram for TCn
Note: The “n” in the register and bit names indicates the device number (n = 1, 3, 4 for Timer/Counter 1, 3, 4), and the “x” indicates output compare unit (A/B).

When a change of the logic level (an event) occurs on the input capture pin (ICPn), or alternatively on the Analog Comparator Output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered: the 16-bit value of the counter (TCNTn) is written to the Input Capture Register (ICRn). The Input Capture Flag (ICF) is set at the same system clock cycle as the TCNTn value is copied into the ICRn . If enabled (TIMSKn.ICIE=1), the Input capture flag generates an input capture interrupt. The ICFn is automatically cleared when the interrupt is executed. Alternatively, the ICF can be cleared by software by writing '1' to its I/O bit location.

Reading the 16-bit value in the ICRn is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read form ICRnL, the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP register.

The ICRn can only be written when using a Waveform Generation mode that utilizes the ICRn for defining the counter’s TOP value. In these cases the Waveform Generation mode bits (WGMn[3:0]) must be set before the TOP value can be written to the ICRn. When writing the ICRn, the high byte must be written to the ICRnH I/O location before the low byte is written to ICRnL.