2.7.2 PCI Express

PCIe is a high speed, packet-based, point-to-point, low pin count, and serial inter connectbus. The IGLOO 2 family has two hard high-speed serial interface blocks. Each SerDes block contains a PCIe system block. The PCIe system is connected to the SerDes block. The following list provides the main supported features:

• Supports ×1, ×2, and ×4 lane configuration
• Endpoint configuration only
• PCI express base specification revision 2.0
• 2.5 Gbps and 5.0 Gbps compliant
• Embedded receive (2 KB), transmit (1 KB) and retry (1 KB) buffer dual-port RAM implementation
• Up to 2 KB maximum payload size
• 64-bitAXI or 32-bit/64-bit AHBL Host and Client interface to the application layer
• 32-bitAPB interface to access configuration and status registers of PCIe system
• Up to 3 x 64 bit base address registers
• 1 Virtual Channel (VC)