2.7.1 SerDes Interface

IGLOO 2 FPGA has up to four 5 Gbps SerDes transceivers, each supports the following features:

• Four SerDes/PCS lanes
• The native EPCS SerDes interface facilitates implementation of serial rapid IO (SRIO) in fabric or a SGMII interface for a soft Ethernet MAC. In EPCS modes, the maximum SerDes rate is 3.2 Gbps.