2.5.1 DDR Bridge

The DDR bridge is a data bridge between two AHB bus hosts and a single AXI bus client. The DDR bridge accumulates AHB writes into write combining buffers prior to bursting out to the external DDR memory. The DDR bridge also includes read combining buffers, allowing AHB hosts to efficiently read data from the external DDR memory from a local buffer. The DDR bridge optimizes reads and writes from multiple hosts to a single external DDR memory. Data coherency rules between the hosts and the external DDR memory are implemented in hardware. The DDR bridge contains two write combining buffers and two read buffers. All buffers within the DDR bridge are implemented with SEU tolerant latches and are not subject to SEUs that SRAM exhibits. IGLOO2 devices implement three DDR bridges in the HPMS, FDDR, and MDDR subsystems.