When the INT0 bit is
set ('1') and the I-bit in the Status Register (SREG) is set ('1'), the external pin
interrupt is enabled. The Interrupt Sense Control 0 bits in the External Interrupt
Control Register A (EICRA.ISC0) define whether the external interrupt is activated
on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin
will cause an interrupt request even if INT0 is configured as an output. The
corresponding interrupt of External Interrupt Request 0 is executed from the INT0
Interrupt Vector.
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