59.2.9 Memory Controllers
| Signal Name | Recommended Pin Connection | Description | |
|---|---|---|---|
| External Bus Interface | |||
| D[15:0] | Application dependent. | Data Bus (D0 to D15) All data lines are pull-up inputs to VDDIO at reset. |
|
| A[23:0] | Application dependent. | Address Bus (A0 to A23) All address lines pull-up inputs to VDDIO at reset. |
|
| NWAIT | Application dependent. | External Wait Signal. Pulled-up input (100 kOhm) to VDDIO at reset. |
|
| Static Memory Controller | |||
| NCS0-NCS3 | Application dependent. (Pullup at VDDIO) |
Chip Select Lines All are pulled-up inputs (100 kOhm) to VDDIO at reset. |
|
| NRD | Application dependent. | Read Signal Pulled-up input (100 kOhm) to VDDIO at reset. |
|
| NWE | Application dependent. | Write Enable All are pulled-up inputs (100 kOhm) to VDDIO at reset. |
|
| NWR0–NWR1 | Application dependent. | Write Signals All are pulled-up inputs (100 kOhm) to VDDIO at reset. |
|
| NBS0–NBS1 | Application dependent. | Byte Mask Signals All are pulled-up inputs (100 kOhm) to VDDIO at reset. |
|
| NAND Flash Logic | |||
| NANDOE | Application dependent. | NAND Flash Output Enable Pulled-up input (100 kOhm) to VDDIO at reset. |
|
| NANDWE | Application dependent. | NAND Flash Write Enable Pulled-up input (100 kOhm) to VDDIO at reset. |
|
