57.13.1.10.1 USART SPI Timings

Timings are given for the 3.3V domain, with VDDIO from 2.85V to 3.6V, maximum external capacitor = 40 pF.

Table 57-60. USART SPI Timings
Symbol	Parameter	Min	Max	Unit
Host Mode
SPI₀	SCK Period	MCK/6	–	ns
SPI₁	Input Data Setup Time	2.5	–	ns
SPI₂	Input Data Hold Time	0.2	–	ns
SPI₃	Chip Select Active to Serial Clock	-0.9	–	ns
SPI₄	Output Data Setup Time	-1.9	10.4	ns
SPI₅	Serial Clock to Chip Select Inactive	-2.4	-1.9	ns
Client Mode
SPI₆	SCK falling to MISO	2.9	13.9	ns
SPI₇	MOSI Setup time before SCK rises	2.0	–	ns
SPI₈	MOSI Hold time after SCK rises	0.2	–	ns
SPI₉	SCK rising to MISO	3.0	13.5	ns
SPI₁₀	MOSI Setup time before SCK falls	2.1	–	ns
SPI₁₁	MOSI Hold time after SCK falls	0.4	–	ns
SPI₁₂	NPCS0 setup to SCK rising	0.6	–	ns
SPI₁₃	NPCS0 hold after SCK falling	0.6	–	ns
SPI₁₄	NPCS0 setup to SCK falling	0.6	–	ns
SPI₁₅	NPCS0 hold after SCK rising	0.7	–	ns