57.13.1.10.1 USART SPI Timings

Timings are given for the 3.3V domain, with VDDIO from 2.85V to 3.6V, maximum external capacitor = 40 pF.

Table 57-60. USART SPI Timings
Symbol Parameter Min Max Unit
Host Mode
SPI0 SCK Period MCK/6 ns
SPI1 Input Data Setup Time 2.5 ns
SPI2 Input Data Hold Time 0.2 ns
SPI3 Chip Select Active to Serial Clock -0.9 ns
SPI4 Output Data Setup Time -1.9 10.4 ns
SPI5 Serial Clock to Chip Select Inactive -2.4 -1.9 ns
Client Mode
SPI6 SCK falling to MISO 2.9 13.9 ns
SPI7 MOSI Setup time before SCK rises 2.0 ns
SPI8 MOSI Hold time after SCK rises 0.2 ns
SPI9 SCK rising to MISO 3.0 13.5 ns
SPI10 MOSI Setup time before SCK falls 2.1 ns
SPI11 MOSI Hold time after SCK falls 0.4 ns
SPI12 NPCS0 setup to SCK rising 0.6 ns
SPI13 NPCS0 hold after SCK falling 0.6 ns
SPI14 NPCS0 setup to SCK falling 0.6 ns
SPI15 NPCS0 hold after SCK rising 0.7 ns