5.2 How to Use SmartBERT

After programming the SmartBERT IP design, double click Generate SmartDebug FPGA Array Data to generate SmartDebug data and double click SmartDebug Design in the Design Flow window, see the following figure.

Figure 5-3. Launching SmartDebug Design Tools

The SmartDebug window is displayed, as shown in the following figure.

To access the debug transceiver feature, select Debug TRANSCEIVER in the SmartDebug window.

Figure 5-4. SmartDebug Window Debug Options

To run Smart BERT in Debug TRANSCEIVER, perform the following steps:

  1. Select the Smart BERT tab in the Debug TRANSCEIVER window.
  2. Select the Pattern from the drop-down list.
    Figure 5-5. Debug TRANSCEIVER—Pattern Selection
  3. Click Start. It enables both transmitter and the receiver for a particular lane and for a particular PRBS pattern. The following figure shows the status of the TXPLL, RXPLL, Lock to Data, Data rate, and the BER.
    Figure 5-6. Debug TRANSCEIVER—Status
    When a SmartBERT IP lane is added, the Error Injection column is displayed in the right pane. The error injection feature is provided to inject an error while running a PRBS pattern.
  4. Click Reset to clear the error count under Cumulative Error Count. Error Count is displayed when the lane is added.

The following figure shows the Smart BERT tab with error count incremented using Inject Error in the Debug TRANSCEIVER window.

Figure 5-7. Smart BERT—Cumulative Error Count

For more information about Debug transceiver features, see AN4594: Debugging PolarFire FPGA Using SmartDebug.

Important: If any of the probe points in SmartBERT tab are not working as expected, see Appendix: Known Issues section in AN4594: Debugging PolarFire FPGA Using SmartDebug.

The SmartBERT reference design is configured for 5 Gbps transceiver data rate. Separate programming files (*.job) and corresponding design Debug Data Container (DDC) are exported from Libero and provided in the following locations:

  • *.job file: mpf_an4662_df/Programming_File
  • *.ddc file: mpf_an4662_df/Source_File

Launch SmartDebug in standalone mode and import the DDC file to access all debug features.

To import *.ddc file in standalone SmartDebug, perform the following steps.

  1. Launch SmartDebug in standalone mode.
  2. In the SmartDebug window, click Project > New Project. The Create SmartDebug Project dialog box opens, see the following figure.
  3. Select the Import from DDC File in the Create SmartDebug Project dialog box and browse the *.ddc file. The design debug data of the target device, all hardware, and JTAG chain information present in the DDC file exported from Libero are automatically inherited by the SmartDebug project.
Figure 5-8. Create SmartDebug Project

For more information about how to export DDC file from Libero, see AN4594: Debugging PolarFire FPGA Using SmartDebug.