AN4662

5.1.2 Port Description

The following table lists the important ports for the design.

Table 5-1. Port List for the CoreSmartBERT IP Design
Port	Direction	Description
LANE0_RXD_P	Input	Transceiver Receiver differential input
LANE0_RXD_N	Input	Transceiver Receiver differential input
REF_CLK_PAD_P	Input	Transmit PLL input clock from reference clock interface
REF_CLK_PAD_N	Input	Transmit PLL input clock from reference clock interface
LANE0_TXD_P	Output	Transceiver Transmitter differential output
LANE0_TXD_N	Output	Transceiver Transmitter differential output

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