9.3 Selectable Duty Cycle

The DC bits in the CLKRCON register are used to modify the duty cycle of the output clock. A duty cycle of 0%, 25%, 50%, or 75% can be selected for all clock rates when the DIV value is not 000. When DIV = 000, the duty cycle defaults to 50% for all values of DC except 00, in which case the duty cycle is 0% (constant low output).

Important: The DC value at Reset is 10. This makes the default duty cycle 50% and not 0%.
Important: Clock dividers and clock duty cycles can be changed while the module is enabled but doing so may cause glitches to occur on the output. To avoid possible glitches, clock dividers and clock duty cycles may be changed only when the module is disabled (EN = 0).