The individual bytes in this
multibyte register can be accessed with the following register names:
NCOxINCU: Accesses the
upper byte INC[19:16]
NCOxINCH: Accesses the
high byte INC[15:8]
NCOxINCL: Accesses the
low byte INC[7:0]
The logical increment spans
NCOxINCU:NCOxINCH:NCOxINCL.
NCOxINC is double-buffered as
INCBUF.
INCBUF is updated on the
next falling edge of NCOxCLK after writing to NCOxINCL
NCOxINCU and NCOxINCH
must be written prior to writing NCOxINCL
Name:
NCOxINC
Offset:
0x058F
Bit
23
22
21
20
19
18
17
16
INC[19:16]
Access
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit
15
14
13
12
11
10
9
8
INC[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
INC[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 19:0 – INC[19:0]
Value by which the NCOxACC is increased by each NCO
clock(1,2)
The individual bytes in this
multibyte register can be accessed with the following register names:
NCOxINCU: Accesses the
upper byte INC[19:16]
NCOxINCH: Accesses the
high byte INC[15:8]
NCOxINCL: Accesses the
low byte INC[7:0]
The logical increment spans
NCOxINCU:NCOxINCH:NCOxINCL.
NCOxINC is double-buffered as
INCBUF.
INCBUF is updated on the
next falling edge of NCOxCLK after writing to NCOxINCL
NCOxINCU and NCOxINCH
must be written prior to writing NCOxINCL
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
