17.8.1 Interrupt Enable Clear
| Name: | INTENCLR |
| Offset: | 0x00 |
| Reset: | 0x00000000 |
| Property: | Write-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DPLLLTO | DPLLLCKF | ||||||||
| Access | R | R | R | R | R | R | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DPLLLCKR | B33SRDY | BOD33DET | BOD33RDY | DFLLRCS | |||||
| Access | R/W | R | R | R | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DFLLLCKC | DFLLLCKF | DFLLOOB | DFLLRDY | OSC8MRDY | OSC32KRDY | XOSC32KRDY | XOSCRDY | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 17 – DPLLLTO DPLL Lock Timeout Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DPLL Lock Timeout Interrupt Enable bit, which disables the DPLL Lock Timeout interrupt.
| Value | Description |
|---|---|
| 0 | The DPLL Lock Timeout interrupt is disabled. |
| 1 | The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Timeout Interrupt flag is set. |
Bit 16 – DPLLLCKF DPLL Lock Fall Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DPLL Lock Fall Interrupt Enable bit, which disables the DPLL Lock Fall interrupt.
| Value | Description |
|---|---|
| 0 | The DPLL Lock Fall interrupt is disabled. |
| 1 | The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Fall Interrupt flag is set. |
Bit 15 – DPLLLCKR DPLL Lock Rise Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DPLL Lock Rise Interrupt Enable bit, which disables the DPLL Lock Rise interrupt.
| Value | Description |
|---|---|
| 0 | The DPLL Lock Rise interrupt is disabled. |
| 1 | The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Rise Interrupt flag is set. |
Bit 11 – B33SRDY BOD33 Synchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the BOD33 Synchronization Ready Interrupt Enable bit, which disables the BOD33 Synchronization Ready interrupt.
| Value | Description |
|---|---|
| 0 | The BOD33 Synchronization Ready interrupt is disabled. |
| 1 | The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Synchronization Ready Interrupt flag is set. |
Bit 10 – BOD33DET BOD33 Detection Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the BOD33 Detection Interrupt Enable bit, which disables the BOD33 Detection interrupt.
| Value | Description |
|---|---|
| 0 | The BOD33 Detection interrupt is disabled. |
| 1 | The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33 Detection Interrupt flag is set. |
Bit 9 – BOD33RDY BOD33 Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the BOD33 Ready Interrupt Enable bit, which disables the BOD33 Ready interrupt.
| Value | Description |
|---|---|
| 0 | The BOD33 Ready interrupt is disabled. |
| 1 | The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Ready Interrupt flag is set. |
Bit 8 – DFLLRCS DFLL Reference Clock Stopped Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Reference Clock Stopped Interrupt Enable bit, which disables the DFLL Reference Clock Stopped interrupt.
| Value | Description |
|---|---|
| 0 | The DFLL Reference Clock Stopped interrupt is disabled. |
| 1 | The DFLL Reference Clock Stopped interrupt is enabled, and an interrupt request will be generated when the DFLL Reference Clock Stopped Interrupt flag is set. |
Bit 7 – DFLLLCKC DFLL Lock Coarse Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Lock Coarse Interrupt Enable bit, which disables the DFLL Lock Coarse interrupt.
| Value | Description |
|---|---|
| 0 | The DFLL Lock Coarse interrupt is disabled. |
| 1 | The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Coarse Interrupt flag is set. |
Bit 6 – DFLLLCKF DFLL Lock Fine Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Lock Fine Interrupt Enable bit, which disables the DFLL Lock Fine interrupt.
| Value | Description |
|---|---|
| 0 | The DFLL Lock Fine interrupt is disabled. |
| 1 | The DFLL Lock Fine interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Fine Interrupt flag is set. |
Bit 5 – DFLLOOB DFLL Out Of Bounds Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Out Of Bounds Interrupt Enable bit, which disables the DFLL Out Of Bounds interrupt.
| Value | Description |
|---|---|
| 0 | The DFLL Out Of Bounds interrupt is disabled. |
| 1 | The DFLL Out Of Bounds interrupt is enabled, and an interrupt request will be generated when the DFLL Out Of Bounds Interrupt flag is set. |
Bit 4 – DFLLRDY DFLL Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Ready Interrupt Enable bit, which disables the DFLL Ready interrupt.
| Value | Description |
|---|---|
| 0 | The DFLL Ready interrupt is disabled. |
| 1 | The DFLL Ready interrupt is enabled, and an interrupt request will be generated when the DFLL Ready Interrupt flag is set. |
Bit 3 – OSC8MRDY OSC8M Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the OSC8M Ready Interrupt Enable bit, which disables the OSC8M Ready interrupt.
| Value | Description |
|---|---|
| 0 | The OSC8M Ready interrupt is disabled. |
| 1 | The OSC8M Ready interrupt is enabled, and an interrupt request will be generated when the OSC8M Ready Interrupt flag is set. |
Bit 2 – OSC32KRDY OSC32K Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the OSC32K Ready Interrupt Enable bit, which disables the OSC32K Ready interrupt.
| Value | Description |
|---|---|
| 0 | The OSC32K Ready interrupt is disabled. |
| 1 | The OSC32K Ready interrupt is enabled, and an interrupt request will be generated when the OSC32K Ready Interrupt flag is set. |
Bit 1 – XOSC32KRDY XOSC32K Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the XOSC32K Ready Interrupt Enable bit, which disables the XOSC32K Ready interrupt.
| Value | Description |
|---|---|
| 0 | The XOSC32K Ready interrupt is disabled. |
| 1 | The XOSC32K Ready interrupt is enabled, and an interrupt request will be generated when the XOSC32K Ready Interrupt flag is set. |
Bit 0 – XOSCRDY XOSC Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the XOSC Ready Interrupt Enable bit, which disables the XOSC Ready interrupt.
| Value | Description |
|---|---|
| 0 | The XOSC Ready interrupt is disabled. |
| 1 | The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC Ready Interrupt flag is set. |