17.8.17 DPLL Control A
| Name: | DPLLCTRLA |
| Offset: | 0x44 |
| Reset: | 0x80 |
| Property: | Write-Protected |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ONDEMAND | RUNSTDBY | ENABLE | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 1 | 0 | 0 |
Bit 7 – ONDEMAND On Demand Clock Activation
| Value | Description |
|---|---|
| 0 | The DPLL is always on when enabled. |
| 1 | The DPLL is activated only when a peripheral request the DPLL as a source clock. The DPLLCTRLA.ENABLE bit must be one to validate that operation, otherwise the peripheral request has no effect. |
Bit 6 – RUNSTDBY Run in Standby
| Value | Description |
|---|---|
| 0 | The DPLL is disabled in standby sleep mode. |
| 1 | The DPLL is not stopped in standby sleep mode. |
Bit 1 – ENABLE DPLL Enable
The software operation of enabling or disabling the DPLL takes a few clock cycles, so check the DPLLSTATUS.ENABLE status bit to identify when the DPLL is successfully activated or disabled.
| Value | Description |
|---|---|
| 0 | The DPLL is disabled. |
| 1 | The DPLL is enabled. |