26.7.8 Voltage Regulator System (VREG) Control
Note: During normal operation, all
voltage regulators that are in use must be left in the On state to allow for the
proper transition between different low-power or standby states.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | VREGCTRL |
| Offset: | 0x001C |
| Reset: | 0x00000004 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| AVREGSTDBY | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| AVREGEN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CPEN[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LVHIB | LVSTDBY | OFFSTDBY | |||||||
| Access | R/W/HC | R/W/HC | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 24 – AVREGSTDBY Additional Voltage Regulator Configuration
| Value | Description |
|---|---|
| 0x0 | USB regulator is off in Sleep, Standby, Hibernate or Backup mode. |
| 0x1 | USB regulator is ON in Standby mode if the AVREGEN bit is set. It is OFF in Hibernate or Backup mode. |
Bit 16 – AVREGEN Additional Voltage Regulator Enabled
| Value | Description |
|---|---|
| 0x0 | USB regulator is disabled (Default) |
| 0x1 | USB regulator is Enabled |
Bits 9:8 – CPEN[1:0] Analog Peripheral Charge Pump Enabled
| Value | Description | Requirements |
|---|---|---|
| 0x0 | All charge pumps disabled. | AVDD ≥ 2.5v |
| 0x1 | Enable charge pump for I/O analog mux and Analog Comparator (AC) | AVDD < 2.5v |
| --- | Reserved | |
| 0x3 | Enable charge pumps for I/O, AC, ADC, and PTC |
Note:
- When AVDD < 2.5v the corresponding appropriate CPEN must be enabled.
- Users must have previously enabled the charge pump clocks defined in Configuration Register 5, FUCFG5.
Bit 5 – LVHIB Low Voltage Hibernate Enable
Note: LVHIB must always be forced to 1.
| Value | Description |
|---|---|
| 0x0 | In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 1.2v. |
| 0x1 | In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 0.8v |
Bit 4 – LVSTDBY Low Voltage Standby Enable
| Value | Description |
|---|---|
| 0x0 | In Standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and optionally VDDCOREUSB/PLL are set to 1.2v. |
| 0x1 | In Standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and operationally VDDCOREUSB/PLL are set to 0.8v. |
Bit 2 – OFFSTDBY Off in Standby Control VREGSW 0 and 1
| Value | Description |
|---|---|
| 0x0 | In Standby mode, VREGSW 0,1 are OFF |
| 0x1 | In standby mode, VREGSW 0,1 are ON |