26.7.7 LVD Control
Note: The LVD comparator is testing for a threshold on the VDDIO supply.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | LVD |
| Offset: | 0x0018 |
| Reset: | 0x00000000 |
| Property: | PAC Write Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| LEVEL[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | OEVEN | DIR | ENABLE | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 19:16 – LEVEL[3:0] Threshold Level.
Refer to REG 52 in 51.3 Power Supply.
Bit 4 – RUNSTDBY Run During Standby
| Value | Description |
|---|---|
| 0 | Run during standby disabled |
| 1 | Run during standby enabled |
Bit 3 – OEVEN Output Event Enable
| Value | Description |
|---|---|
| 0 | Output events disabled |
| 1 | Output events enabled |
Bit 2 – DIR Detection Direction
| Value | Description |
|---|---|
| 0 | Rising detection |
| 1 | Falling detection |
Bit 1 – ENABLE Enable Low Voltage Detection
| Value | Description |
|---|---|
| 0 | Low Voltage Detection disabled |
| 1 | Low Voltage Detection enabled |