25.9.1 DMA Control A Register
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ENABLE | |||||||||
| Access | R/W | ||||||||
| Reset | 1 |
Bit 1 – ENABLE DMA Enable
If the DMA is enabled and this bit is written to zero, the DMA may have outstanding bus transactions that need to complete before it can completely disable.
| Value | Description |
|---|---|
| 0 | DMA module and channels are disabled |
| 1 | DMA module and channels are enabled |