25.9.3 Debug Control Register
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | DBGCTRL |
Offset: | 0x08 |
Reset: | 0x00000000 |
Property: | PAC Write-Protection |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
DBGRUN | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit 0 – DBGRUN Debug Run
This bit controls the DMA functionality when the CPU is halted by an external debugger.
Note: The user should be certain to set this field if he wishes the DMA to operate
normally during debug.
Value | Description |
---|---|
0 | DMA halts the operation during debug. All outstanding bus requests complete before halting. |
1 | DMA continues the normal operation during debug. |