25.9.2 DMA Control B Register

Table 25-7. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CTRLB
Offset:	0x04
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
							QOS2[1:0]
Access							R/W	R/W
Reset							0	0


Bit	15	14	13	12	11	10	9	8
							QOS1[1:0]
Access							R/W	R/W
Reset							0	0


Bit	7	6	5	4	3	2	1	0
							QOS0[1:0]
Access							R/W	R/W
Reset							0	0

Bits 0:1, 8:9, 16:17 – QOSn Priority Group n QOS control [n=1..3]

Sets the Quality of service level for Channel Priority Group n. Setting this value affects arbitration within the device bus fabric. This value does not affect arbitration within the DMA.

Note: DMA0 has 3 priority levels, DMA1 has 2 priority levels.

Table 25-8. Generator Clock Source Selection
Value	Name	Description
0x0	LEVEL_0	QoS level is 0 (lowest)
0x1	LEVEL_1	QoS level is 1 (lower)
0x2	LEVEL_2	QoS level is 2 (medium)
0x3	LEVEL_3	QoS level is 3 (high)