1.4.1 12-Bit Core Device Simulation - PIC10/12/16

The following topics discuss the 12-bit core device features modeled in the simulator.

12-Bit Core CPU

Reset Conditions

All Reset conditions are supported by the simulator. The types of resets available by selecting Debug>Reset are:

  • MCLR Reset
  • Watchdog Timer Reset
  • Brown Out Reset
  • Processor Reset F6

The Time-out (TO) and Power-down (PD) bits in the STATUS register reflect appropriate Reset condition. This feature is useful for simulating various power-up and time-out forks in your code.

Watchdog Timer

The Watchdog Timer is fully simulated in the simulator.

The period of the WDT is determined by the pre/postscaler settings in the OPTION_REG register. The minimum period (with pre/postscaler at 1:1) may be set in the File>Project Properties dialog, “Simulator” category, “Break Options” option category.

The WDT is enabled/disabled in code.

A WDT time-out is simulated when WDT is enabled, proper pre/postscaler is set and WDT actually overflows.

(Future Feature) On WDT time-out, the simulator will halt or Reset, depending on the selection in the “Break Options” option category.

12-Bit Core Peripherals

Along with core support, the simulator fully supports the peripherals in the following sections.

TIMER0

Timer0 timer/counter module in both internal and external clock modes is fully supported. The Timer0 interrupt on overflow is fully supported. Delay from external clock edge to timer increment has also been simulated, as well as the interrupt latency period. Clock input must have a minimum high time of 1 Tcy and a minimum low time of 1 Tcy due to the stimulus file requirements.

Note: It is important to remember that, because the simulator executes on instruction cycle boundaries, resolutions below 1 Tcy cannot be simulated.

A/D Converter

All the registers, timing function and interrupt generation are implemented. The simulator, however, does not load any meaningful value into the A/D result register (ADRES) at the end of a conversion unless a stimulus injection file has been attached to ADRES (L). The simulator will produce a warning in the Output window if a conversion is initiated but no input data is available.

Pins selected as analog (in the ADCON or ADCON1 register) are set as inputs in the corresponding port latch register. This is to accommodate simulator stimulus.

Because simulation is to the register level, and not the pin level, bit/pin names will be read as ‘0’, as required for analog, although injected stimulus may have actually changed the value to ‘1’.

Note: If you have trouble with I/O pins on processors that have A/D, make certain that the A/D pin control registers (ADCON registers) are configuring those pins for digital I/O rather than for analog input. For most processors, these default to analog inputs and the associated pins cannot be used for I/O until the ADCON (or ADCON1) register is set properly.

Comparators

Only comparator modes that do not use Vref are simulated.

Because simulation is to the register level, and not the pin level, bit/pin names will be read as ‘0’, as required for analog, although injected stimulus may have actually changed the value to ‘1’.

Toggling a comparator pin will not work since toggling involves reading a value and inverting it. Since the value always reads ‘0’, the bit/pin never toggles. Instead, use two statements to toggle a comparator pin, e.g.,

  • RA1 set low
  • RA1 set high

EEPROM Data Memory

The EEPROM data memory is fully simulated. The registers and the read/write cycles are fully implemented. The write cycle time is device dependent (to nearest instruction cycle multiple).

The simulator simulates the functions of WRERR and WREN control bits in the EECON1 register. WRERR can be set using stimulus for testing purposes.

OSC Control of IO

The I/O pins are controlled for I/O depending on oscillator settings and whether the oscillator uses the pins.

IO Ports

All I/O ports are supported for input/output, interrupt and change events. The I/O is supported to a register level and not a pin level.