1.4.3 16-Bit Core Device Simulation – PIC18

The following topics discuss the enhanced 16-bit core device features modeled in the simulator.

16-Bit Cor (PIC18) Interrupts

The following interrupts are supported:

  • External interrupt on INT pin
  • TMR0 overflow interrupt
  • External interrupt on RA0 pin
  • Port B input change interrupt
  • Timers/Counters
  • CCP/ECCP
  • PWM
  • A/D
  • Comparators
  • EEPROM
  • UARTS

16-Bit Core (PIC18) CPU

Reset Conditions

All Reset conditions are supported by the simulator.

The Time out (TO) and Power-Down (PD) bits in the RCON register reflect appropriate Reset condition. This feature is useful for simulating various power-up and time-out forks in the user code.

You cannot Reset by toggling notMCLR using stimulus control. You must use Debug> Reset>MCLR Reset.

Sleep

When executing a Sleep instruction, the simulator will appear “asleep” until a wake-up from sleep condition occurs. For example, if the Watchdog Timer has been enabled, it will wake the processor up from sleep when it times out (depending upon the pre/postscaler setting).

An example of a wake-up-from-sleep condition would be an input change on Port B. If the interrupt is enabled (RBIE) and the priority bit (RBIP) is selected, the processor will wake up and will resume executing from the instruction following the Sleep command.

Watchdog Timer

The Watchdog Timer is fully simulated in the simulator.

The period of the WDT is determined by the pre/postscaler Configuration bits WDTPS0:2. The minimum period (with pre/postscaler at 1:1) may be set in the configuration bits in code.

Setting the Configuration bit WDTEN to ‘0’ will disable the WDT, unless it is enabled by the SWDTEN bit of the WDTCON register. Setting the Configuration bit WDTEN to ‘1’ will enable the WDT regardless of the value of the SWDTEN bit.

The WDT is enabled/disabled in code.

A WDT time-out is simulated when WDT is enabled, proper pre/postscaler is set and WDT actually overflows.

(Future Feature) On WDT time-out, the simulator will halt or Reset, depending on the selection in the File>Project Properties dialog, “Simulator” category, “Break Options” option category.

16-Bit Core (PIC18) Processor Modes

The following processor modes are supported by the simulator for devices which allow them:

  • Microcontroller (Default)
  • Extended Microcontroller
  • Microprocessor
  • Microprocessor with Boot Block

For information on external memory, see Section 2.6 “Using External Memory”.

16-Bit Core (PIC18) Special Registers

To aid in debugging this device, certain items that are normally not observable have been declared as “special” registers. Prescalers cannot be declared in user code as “registers”, so the following special symbols are available in the Special Function Registers window:

  • T0PRE (Prescaler for Timer 0)
  • WDTPRE (Prescaler for WDT)

16-Bit Core (PIC18) Peripherals

Along with core support, the simulator supports the following peripheral modules, in addition to general purpose I/O.

The delays and interrupt latency are implemented on all peripherals.

Timers

Timer0 (and the interrupt it can generate on overflow) is fully supported, and will increment by the internal or external clock. Clock input must have a minimum high time of 1 Tcy and a minimum low time of 1 Tcy due to stimulus requirements.

All Other Timers in their various modes are supported, except for modes using an external crystal. The simulator supports Timer interrupts generated on overflow, and interrupts generated by wake-up from sleep. Although the external oscillator is not simulated, a clock stimulus can be assigned to those pins. The prescaler for TimerX is made accessible as TXPRE in the SFR window.

CCP/ECCP

Capture

The simulator fully supports capture and the interrupt generated.

Compare

The simulator supports compare mode, its interrupt and the special event trigger (resetting a Timer by CCP).

PWM

PWM output is fully supported (resolution greater than 1 Tcy only) except for Dead Band delay.

PWM

PWM output is fully supported (resolution greater than 1 Tcy only) except for Dead Band delay.

Comparators

Only comparator modes that do not use Vref are simulated.

Because simulation is to the register level, and not the pin level, bit/pin names will be read as ‘0’, as required for analog, although injected stimulus may have actually changed the value to ‘1’.

Toggling a comparator pin will not work since toggling involves reading a value and inverting it. Since the value always reads ‘0’, the bit/pin never toggles. Instead, use two statements to toggle a comparator pin, e.g.,

  • RA1 set low
  • RA1 set high

A/D Converter

All the registers, timing function and interrupt generation are implemented. The simulator, however, does not load any meaningful value into the A/D result registers (ADRES) at the end of a conversion. A read of the A/D registers will load this data into the registers.

Pins selected as analog (in the ADCON register) are set as inputs in the corresponding port latch register. This is to accommodate simulator stimulus.

Because simulation is to the register level, and not the pin level, bit/pin names will be read as ‘0’, as required for analog, although injected stimulus may have actually changed the value to ‘1’.

Note: If you have trouble with I/O pins on processors that have A/D, make certain that the ADCON registers are configuring those pins for digital I/O rather than for analog input. For most processors, these default to analog inputs and the associated pins cannot be used for I/O until the ADCON registers are set properly.

USART

USART functionality is supported. The following limitations apply to USART operations:

  • The receiver register must be stimulated using a message-based stimulus file. The characters are clocked into the receiver register at the default or current baud rate, starting at the time defined within the message-based stimulus file. If the receiver is not enabled when the data starts arriving, the data is lost.

EEPROM Data Memory

The EEPROM data memory is fully simulated. The registers and the read/write cycles are fully implemented. The write cycle time is device dependent (to nearest instruction cycle multiple).

The simulator simulates the functions of WRERR and WREN control bits in the EECON1 register. WRERR can be set using stimulus for testing purposes.

Peripheral Remapping Functionality

The remapping of I/O pins is fully supported. The lock/unlock functionality to change the mappings is also supported.

OSC Control of IO

The I/O pins are controlled for I/O depending on oscillator settings and whether the oscillator uses the pins.

IO Ports

All I/O ports are supported for input/output, interrupt and change events. The I/O is supported to a register level and not a pin level.