1.4.2 14-Bit Core Device Simulation - PIC12/16

The following topics discuss the 14-bit core device features modeled in the simulator.

14-Bit Core Interrupts

The following interrupts are supported:

  • Timers
  • CCP/ECCP
  • UARTS
  • Change on Port RB <7:4>
  • External interrupt from RB0/INT pin
  • Comparators
  • A/D converter
  • EEPROM write complete

14-Bit Core CPU

Reset Conditions

All Reset conditions are supported by the simulator.

The Time-out (TO) and Power-down (PD) bits in the STATUS register reflect appropriate Reset condition. This feature is useful for simulating various power-up and time-out forks in the user code.

A MCLR Reset during normal operation or during Sleep can easily be simulated by driving the MCLR pin low (and then high) via stimulus or by selecting Debug> Reset>MCLR Reset.

Sleep

When executing a Sleep instruction, the simulator will appear “asleep” until a wake-up from sleep condition occurs. For example, if the Watchdog Timer has been enabled, it will wake the processor up from sleep when it times out (depending upon the pre/postscaler setting).

An example of a wake-up-from-sleep condition would be Timer1 wake up from sleep. In this case, when the processor is asleep, Timer1 would continue to increment until it overflows. If the interrupt is enabled, the timer will wake the processor on overflow and branch to the interrupt vector.

Watchdog Timer

The Watchdog Timer is fully simulated in the simulator.

The period of the WDT is determined by the pre/postscaler settings in the OPTION_REG register. The minimum period (with pre/postscaler at 1:1) may be set in the File>Project Properties dialog, “Simulator” category, “Break Options” option category.

The WDT is enabled/disabled in code.

A WDT time-out is simulated when WDT is enabled, proper pre/postscaler is set and WDT actually overflows.

(Future Feature) On WDT time-out, the simulator will halt or Reset, depending on the “Break Options” option category.

14-Bit Core Peripherals

Along with core support, the simulator supports the following peripheral modules, in addition to general purpose I/O. Consult the data sheet for the particular device you are using for information on which symbols are implemented.

Note: Even if peripheral functionality is not supported in the simulator, the peripheral registers will be available as read/write.

The delays and interrupt latency are implemented on all peripherals.

Timers

Timer0 (and the interrupt it can generate on overflow) is fully supported, and will increment by the internal or external clock. Clock input must have a minimum high time of 1 Tcy and a minimum low time of 1 Tcy due to stimulus requirements.

Timer1 in its various modes is supported, except when running in counter mode by an external crystal. The simulator supports Timer1 interrupts generated on overflow, and interrupts generated by wake-up from sleep. The external oscillator on RC0/RC1 is not simulated, but a clock stimulus can be assigned to those pins.

Timer2 and the interrupt that can be generated on overflow are fully supported.

CCP/ECCP

Capture

The simulator fully supports capture and the interrupt generated.

Compare

The simulator supports compare mode, its interrupt and the special event trigger (resetting Timer1 by CCP1).

PWM

PWM output is fully supported (resolution greater than 1 Tcy only) except for Dead Band delay.

Comparators

Only comparator modes that do not use Vref are simulated.

Because simulation is to the register level, and not the pin level, bit/pin names will be read as ‘0’, as required for analog, although injected stimulus may have actually changed the value to ‘1’.

Toggling a comparator pin will not work since toggling involves reading a value and inverting it. Since the value always reads ‘0’, the bit/pin never toggles. Instead, use two statements to toggle a comparator pin, e.g.,

  • RA1 set low
  • RA1 set high

A/D Converter

All the registers, timing function and interrupt generation are implemented. The simulator, however, does not load any meaningful value into the A/D result register (ADRES) at the end of a conversion unless an injection file has been attached to ADRES (L).

Pins selected as analog (in the ADCON or ADCON1 register) are set as inputs in the corresponding port latch register. This is to accommodate simulator stimulus.

Because simulation is to the register level, and not the pin level, bit/pin names will be read as ‘0’, as required for analog, although injected stimulus may have actually changed the value to ‘1’.

Note: If you have trouble with I/O pins on processors that have A/D, make certain that the A/D pin control registers (ADCON registers) are configuring those pins for digital I/O rather than for analog input. For most processors, these default to analog inputs and the associated pins cannot be used for I/O until the ADCON (or ADCON1) register is set properly.

USART

USART functionality is supported. The following limitations apply to USART operations:

  • The receiver register must be stimulated using a message-based stimulus file. The characters are clocked into the receiver register at the default or current baud rate, starting at the time defined within the message-based stimulus file. If the receiver is not enabled when the data starts arriving, the data is lost.

EEPROM Data Memory

The EEPROM data memory is fully simulated. The registers and the read/write cycles are fully implemented. The write cycle time is device dependent (to nearest instruction cycle multiple).

The simulator simulates the functions of WRERR and WREN control bits in the EECON1 register. WRERR can be set using stimulus for testing purposes.

OSC Control of IO

The I/O pins are controlled for I/O depending on oscillator settings and whether the oscillator uses the pins.

IO Ports

All I/O ports are supported for input/output, interrupt and change events. The I/O is supported to a register level and not a pin level.