1.4.4 24-Bit Core Device Simulation – PIC24 MCUs / dsPIC DSCs

The following topics discuss the PIC24 MCU and dsPIC DSC device features modeled in the simulator.

24-Bit Exceptions (Traps/Interrupts)

The simulator supports all core and peripheral traps and interrupts, even if the peripheral is currently not supported.

The dsPIC DSC core features a vectored exception processing structure for up to 8 traps and 54 interrupts or 62 total independent vectors. Each interrupt is prioritized, based on a user-assigned priority between 1 and 7 (1 being the lowest priority and 7 being the highest). If a conflict occurs (two interrupts at the same priority), interrupt service will be based on a predetermined 'natural order' which is hardware-based.

DMA Transfer Request

In the simulator, you may initiate a DMA transfer request by setting the interrupt source flag in software. For example, if Timer2 is chosen as the source of the DMA transfer request, setting the T2IF bit in the IFS0 register will trigger a DMA transfer.

24-Bit System Integration Block

Reset Sources

All Reset sources are supported by the simulator.

Status bits from the RCON register are set or cleared differently in different Reset situations, as indicated in device data sheet. These bits are used in software to determine the nature of the Reset.

A MCLR Reset during normal operation or during Sleep/Idle can easily be simulated by driving the MCLR pin low (and then high) via stimulus or by selecting Debug> Reset>MCLR Reset.

Sleep/Idle

When executing a PWRSAV instruction, the simulator will appear “asleep” or “idle” until a wake-up condition occurs. For example, if the Watchdog Timer has been enabled, it will wake the processor up from sleep when it times out (depending upon the pre/postscaler setting).

An example of a wake-up-from-sleep condition would be Timer1 wake up from sleep. In this case, when the processor is asleep, Timer1 would continue to increment until it matches the period counter. If the interrupt is enabled, the timer will wake the processor and branch to the interrupt vector.

Watchdog Timer

The Watchdog Timer is fully simulated in the simulator.

The Watchdog Timer can be “Enabled” or “Disabled” through a Configuration bit (FWDTEN) in the Configuration register FWDT. Setting FWDTEN = 1 enables the Watchdog Timer. Setting FWDTEN = 0 allows user software to enable/ disable the Watchdog Timer via the SWDTEN (RCON<5>) control bit.

The period of the WDT is determined by the pre/postscaler settings in the FWDT register. The minimum period (with pre/postscaler at 1:1) may be set in the configuration bits in code.

The WDT is enabled/disabled in code.

A WDT time-out is simulated when WDT is enabled, proper pre/postscaler is set and WDT actually overflows.

(Future Feature) On WDT time-out, the simulator will halt or Reset, depending on the selection in the File>Project Properties dialog, “Simulator” category, “Break Options” option category.

24-Bit Peripherals

The simulator supports the peripherals discussed in the following sections.

The delays and interrupt latency are implemented on all peripherals.

Input Capture

All Input Capture modules are fully supported in all modes.

Output Compare

All Output Compare modules are fully supported in all modes.

Change Notify

All Change Notify functionality and interrupts are supported.

Interrupts

All interrupts are supported. Both vector tables are supported. All interrupts including priority settings are simulated.

OSC Control of IO

The I/O pins are controlled for I/O depending on oscillator settings and whether the oscillator uses the pins.

Timers

All timers are fully supported in all modes. External clock must be a minimum of 1 Tcy. Timers can be combined to create 32-bit counters.

IO Ports

All I/O ports are supported for input/output, interrupt and change events. The I/O is supported to a register level and not a pin level.

Comparators

Because simulation is to the register level, and not the pin level, bit/pin names will be read as ‘0’, as required for analog, although injected stimulus may have actually changed the value to ‘1’.

Toggling a comparator pin will not work since toggling involves reading a value and inverting it. Since the value always reads ‘0’, the bit/pin never toggles. Instead, use two statements to toggle a comparator pin, e.g.,

  • RA1 set low
  • RA1 set high

PWM

PWM output is fully supported (resolution greater than 1 Tcy only) except for Dead Band delay.

A/D Converter

All the registers, timing function and interrupt generation are implemented. To load meaningful data into the A/D result buffer at the end of a conversion, use an injection file (see Section 3.4.6 “Register Injection Tab”).

Pins selected as analog (in the ADPCFG and TRIS registers) are set as inputs in the corresponding port latch register. This is to accommodate simulator stimulus.

Because simulation is to the register level, and not the pin level, bit/pin names will be read as ‘0’, as required for analog, although injected stimulus may have actually changed the value to ‘1’.

Note: If you have trouble with I/O pins on processors that have A/D, make certain that the ADPCFG and TRIS registers are configuring those pins for digital I/O rather than for analog input. For most processors, these default to analog inputs and the associated pins cannot be used for I/O until these registers are set properly.

UART

UART functionality is supported. For more information, see Section 2.6 “Using a USART/UART”.

The following limitations apply to UART operations:

  • The receiver register must be stimulated using a message-based stimulus file. The characters are clocked into the receiver register at the default or current baud rate, starting at the time defined within the message-based stimulus file. If the receiver is not enabled when the data starts arriving, the data is lost. If the receiver is enabled the characters are read into the FIFO buffer until the FIFO is full. If the characters in the FIFO are not read out in time the remaining characters in the stimulus file will be lost and the OV status bit will be set.
  • The transmitter register must be captured using an on-demand stimulus file. When the transmitter is enabled, characters written to the transmitter register are clocked into the transmitter FIFO at the current baud rate. When a character becomes available in the FIFO, it is written to the on-demand response file.
  • The receiver and transmitter FIFOs are not visible to the user.
  • Certain errors can occur due to the fact that the receiver register is stimulated from an on-demand file. The errors are not simulated and receiver buffer overrun error.

Peripheral Pin Mapping Support

The remapping of I/O pins is fully supported. The lock/unlock functionality to change the mappings is also supported.

DMA Mode

The DMA is fully supported for all transfer modes.

EEPROM Data Memory

The EEPROM data memory is fully simulated. The registers and the read/write cycles are fully implemented. The write cycle time is device dependent (to nearest instruction cycle multiple).

The simulator simulates the functions of WRERR and WREN control bits in the EECON1 register. WRERR can be set using stimulus for testing purposes.