1.4.5 32-Bit Core Device Simulation – PIC32M

The following topics discuss the PIC32M MCU device features modeled in the simulator.

32-Bit Exceptions (Traps/Interrupts)

The simulator supports all core and peripheral traps and interrupts, even if the peripheral is currently not supported.

The PIC32 MCU core features a vectored exception processing structure for up to 96 interrupt sources and 63 independent vectors. Each interrupt has group priorities, based on a user-assigned priority between 1 and 7 (1 being the lowest priority and 7 being the highest). In addition there are 2 bits for sub priority within each group, also based on a user-assigned priority between 0 and 3 (0 being the lowest priority and 3 being the highest). Interrupts within a group will not preempt each other. If a conflict occurs (two interrupts at the same priority), interrupt service will be based on a predetermined 'natural order' which is hardware-based, or the user can use the sub priority bits to change the natural order. Traps are handled by the MIPS Core registers.

32-Bit Core (PIC32) CPU

Latency

The simulator is not cycle accurate for PIC32 MCU simulations.

Reset Conditions

All Reset conditions are supported by the simulator.

You cannot Reset by toggling notMCLR using stimulus control. You must use Debug> Reset>MCLR Reset.

Hazard Barrier

The simulator does not support hazard barriers. Therefore instructions such as JR.HB, JALR.HB, and EHB related to Hazard Barrier are simulated as NOP.

Sleep

When executing a Sleep instruction, the simulator will appear “asleep” until a wake-up from sleep condition occurs. For example, if the Watchdog Timer has been enabled, it will wake the processor up from sleep when it times out (depending upon the pre/postscaler setting).

An example of a wake-up-from-sleep condition would be an input change on Port B. If the interrupt is enabled and the priority bit is selected, the processor will wake up and will resume executing from the instruction following the Sleep command.

Watchdog Timer

The Watchdog Timer is fully simulated in the simulator.

The period of the WDT is determined by the pre/postscaler Configuration bits WDTPS0:2. The minimum period (with pre/postscaler at 1:1) may be set in the configuration bits in code.

Setting the Configuration bit WDTEN to ‘0’ will disable the WDT, unless it is enabled by the SWDTEN bit of the WDTCON register. Setting the Configuration bit WDTEN to ‘1’ will enable the WDT regardless of the value of the SWDTEN bit.

The WDT is enabled/disabled in code.

A WDT time-out is simulated when WDT is enabled, proper pre/postscaler is set and WDT actually overflows.

(Future Feature) On WDT time-out, the simulator will halt or Reset, depending on the selection in the File>Project Properties dialog, “Simulator” category, “Break Options” option category.

For information on external memory, see Section 2.6 “Using External Memory”.

32-Bit Core (PIC32) Peripherals

The PIC32 supports the peripheral modules discussed in the following sections.

Input Capture

All Input Capture modules are fully supported in all modes.

Output Compare

All Output Compare modules are fully supported in all modes.

Change Notify

All Change Notify functionality and interrupts are supported.

Interrupts

All interrupts are supported. Both single vectored and multi vectored interrupt modes are supported. All interrupts including priority settings are simulated.

Timers

All timers are fully supported in all modes. External clock must be a minimum of 1 Tcy. Timers can be combined to create 32-bit counters.

IO Ports

All I/O ports are supported for input/output, interrupt and change events. The I/O is supported to a register level and not a pin level.

Comparators

Only comparator modes that do not use Vref are simulated.

Because simulation is to the register level, and not the pin level, bit/pin names will be read as ‘0’, as required for analog, although injected stimulus may have actually changed the value to ‘1’.

Toggling a comparator pin will not work since toggling involves reading a value and inverting it. Since the value always reads ‘0’, the bit/pin never toggles. Instead, use two statements to toggle a comparator pin, e.g.,

  • RA1 set low
  • RA1 set high

PWM

There is no dedicated PWM in PIC32 devices. Output compare operating in PWM mode is fully simulated.

A/D Converter

All the registers, timing function and interrupt generation are implemented. The simulator, however, does not load any meaningful value into the A/D result register (ADRES) at the end of a conversion unless an injection file has been attached to ADRES (L).

Pins selected as analog (in the ADCON or ADCON1 register) are set as inputs in the corresponding port latch register. This is to accommodate simulator stimulus.

Because simulation is to the register level, and not the pin level, bit/pin names will be read as ‘0’, as required for analog, although injected stimulus may have actually changed the value to ‘1’.

Note: If you have trouble with I/O pins on processors that have A/D, make certain that the A/D pin control registers (ADCON registers) are configuring those pins for digital I/O rather than for analog input. For most processors, these default to analog inputs and the associated pins cannot be used for I/O until the ADCON (or ADCON1) register is set properly.

The A/D converter operates on the PB clock which is the CPU clock/PBDIV. For other peripherals, the PB clock is the same as CPU clock. PIC32 devices.

UART

UART functionality is supported. The following limitations apply to UART operations:

  • The receiver register must be stimulated using a message-based stimulus file. The characters are clocked into the receiver register at the default or current baud rate, starting at the time defined within the message-based stimulus file. If the receiver is not enabled when the data starts arriving, the data is lost. If the receiver is enabled the characters are read into the FIFO buffer until the FIFO is full. If the characters in the FIFO are not read out in time the remaining characters in the stimulus file will be lost and the OV status bit will be set.
  • The transmitter register must be captured using an on-demand stimulus file. When the transmitter is enabled, characters written to the transmitter register are clocked into the transmitter FIFO at the current baud rate. When a character becomes available in the FIFO, it is written to the on-demand response file.
  • The receiver and transmitter FIFOs are not visible to the user.
  • Certain errors can occur due to the fact that the receiver register is stimulated from an on-demand file. The errors are not simulated and receiver buffer overrun error.