| Document |
- Device variant for temperature range from -40°C to 105°C
added.
- Change of document style.
- New Microchip document number. Previous version was Atmel
document 42385 rev.J.
|
| Features | Added the temperature range: - -40°C to 85°C
- -40°C to 105°C
|
| I/O Multiplexing and Considerations |
- Table 7-5: No
PB16, PB7 on SAM L21G
|
| PAC - Peripheral Access Controller | Editorial updates. |
| DSU - Device Service Unit | Editorial updates. |
| Clock System | Editorial updates. |
| GCLK - Generic Clock Controller | Editorial updates. |
| RTC – Real-Time Counter |
- Functional
description of General Purpose registers added.
- Bit field
position updated: CTRLB.ACTF, CTRLB.DEBF, SYNCBUSY.GPn.
- Register RTC.PER is at offset 0x1C.
- Editorial updates.
|
| DMAC – Direct Memory Access Controller |
- STEPSIZE factor in SRAM register BTCTRL is based on beat size in
bytes.
- Editorial
updates.
|
| EIC – External Interrupt Controller | Editorial updates. |
| OSCCTRL – Oscillators Controller |
- Register OSCCTRL.DPLLCTRLB is not Enable-protected.
- Editorial updates.
|
| OSC32KCTRL –
32KHz Oscillators Controller | Editorial updates. |
| SUPC – Supply Controller | Editorial updates. |
| WDT – Watchdog Timer |
- Register WDT.CONFIG is not Enable-protected.
- Register WDT.EWCTRL is not Enable-protected.
- Editorial updates.
|
| PORT - I/O Pin
Controller |
- Notes added: PINCFG and PMUX registers are repeated per PORT
group with offset 0x80.
- Bit PORT.CTRL.SAMPLING is write-only.
|
| TC – Timer/Counter |
- Bits ENABLE and SWRST in TC.CTRLA are not enable-protected.
- Register TC.STATUS is read-synchronized.
- Register TC.INTENCLR: "Enable" in bit names replaced by
"Disable".
- Registers TC.CCx are write- and read-synchronized.
- Editorial updates.
|
| TCC – Timer/Counter for Control Applications |
- Register TCC.PER is write-synchronized
- Register TCC.PATT is write-synchronized
- Size of PGVB and PGEB bits in TCC.PATTBUF is 8 bit.
|
| TRNG – True Random Number Generator |
- Register TRNG.DATA has R/W access.
- Register TRNG.EVCTRL is not enable-protected.
|
| AES – Advanced Encryption Standard | Editorial updates. |
| USB – Universal Serial Bus |
- Register USB.FNUM is read-only.
- Register USB.EPSTATUSCLRn is write-only.
- Register USB.EPSTATUSSETn is write-only.
- Register USB.STATUS_PIPE has R/W access.
- Register USB.QOSCTRL has Reset value 0x05.
- Editorial updates.
|
| DAC – Digital-to-Analog Converter |
- Register DAC.CTRLB is not enable-protected.
|
| CCL – Configurable Custom Logic | Editorial updates. |
| Electrical
Characteristics |
- Data for 105°C device variant added.
- Updates for 85°C
device variant:
- Power Consumption table for OSC16M: symbol and
description corrected.
- Operating Conditions table for DAC: Conditions for
VREF simplified.
|
| Errata SAML21 |
Added Errata: - SERCOM: In USART autobaud mode, missing stop bits
are not recognized as inconsistent sync (ISF) or framing
(FERR) errors. Errata reference 13852
- DAC: DAC stepping does not work when data written
from DMA. Errata reference 15210
- EIC: Spurious INTFLAG is raised when EIC is
configured LOW LEVEL with Filter mode. Errata reference
15278
- EIC: Changing the NMI configuration(CONFIGn.SENSEx)
on the fly may lead to a false NMI interrupt. Errata
reference 15279
- ADC: Clock request not going low in standby mode.
Errata reference 15463
- USART: PA24/PA25 pull-up/pull-down configuration
erroneous when used as RTS, CTS. Errata reference
15581
- PORT:
PORT read/write attempts on non-implemented registers,
including addresses beyond the last implemented register
group (PA, PB, …) do not generate a PAC protection error.
Errata reference 15611
- TCC:
Using dithering mode with external retrigger events can lead
to unexpected stretch of right aligned pulses, or shrink of
left aligned pulses. Errata reference 15625
- DMAC:
When using more than one DMA channel and one of them is
w/linked descriptor, a fetch error can appear on this
channel. Errata reference 15670
- DMAC:
When at least one channel w/linked descriptors is already
active, and the channel number of the channel being enabled
is lower than the channel already active, enabling another
DMA channel can result in a channel Fetch Error (FERR) or an
incorrect descriptor fetch. Errata reference
15683
- FDPLL:
When changing on-the-fly the FDPLL ratio in DPLLnRATIO
register, STATUS.DPLLnLDRTO will not be set when the ratio
update will be completed. Errata reference 15753
Errata reference for changed (content of errata
unchanged): - DFLL48M: 16192 (was 10669)
- DFLL48M: 16193 (was 11938)
|
