54.13 Rev C - 03/2015

• Two ACs

• 'BOD12 Enable' renamed to 'BOD12 Disable'
• 'BOD33 Enable' renamed to 'BOD33 Disable'

• Editorial updates
• PTC pins updated for die rev.B
• OPAMP pins updated for die rev.B

• No RFCTRL, ATW, TAL functionality

• Updated Figure 40-5
• Filter delay two to five peripheral clock cycles

• Synchronous Edge Detection mode supports Idle sleep mode
• Editorial updates

• No TAL functionality
• Reset value of APBCMASK register is 0x00007FFF

• Update block diagram

• PLCFG.PLDIS added for die revision B
• STDBYCFG.AVREGSD replaced by STBYCFG.VREGSMOD for die revision B
• Power Domain Partition diagram added
• Editorial updates

• Figure 36-30 added

• DPLLCTRLB register property 'Enable-Protected' added

• Features
• DMAC – Direct Memory Access Controller
• SUPC – Supply Controller
• TC – Timer/Counter
• Operational Amplifier Controller (OPAMP)

Electrical Characteristics:

• Supply Characteristics
• Power Consumption
• Wake-Up Time
• Peripheral Power Consumption
• APWS
• Power-On Reset (POR) Characteristics
• Brown-Out Detectors (BOD) Characteristics
• Operational Amplifier Controller (OPAMP)
• SERCOM I²C – SERCOM Inter-Integrated Circuit
• Analog-to-Digital Converter (ADC) Characteristics
• Digital to Analog Converter (DAC) Characteristics
• Oscillators Characteristics
• DETREF
• OPAMP
• NVM Characteristics

• PTC, OPAMP: PTC pins Y[1:3], Y[5], Y[12] relocated. OPAMP pins OA_OUT[1] and OA_NEG[2] swapped. (This document describes die rev.B.) Errata reference 14046
• SUPC: Under certain conditions, bit VREF.ONDEMAND has no effect. Errata reference 14268
• DAC: Default value of CTRLB increases loading capacitance of pin PA03. (Fixed for die rev.B.) Errata reference 14310
• EVSYS: Synch/resynch path to PORT not functional. (Fixed for die rev.B.) Errata reference 14317

Fixed errata:

• PM: In die rev.A, the wrong voltage regulator was used under certain conditions. (Fixed for die rev.B.) Errata reference 13901