4.1 Simulation Flow

The following steps describe the JESD204B testbench simulation flow:

  1. At the start, the NSYSRESET signal resets all of the components.
  2. After the transceiver block is initialized, the TB_RX_READY signal is asserted high.
  3. The JESD204BRX issues a synchronization request by asserting the TB_SYNC_N low.
  4. The JESD204BTX responds to the request by sending K28.5 characters to the JESD204RX.
  5. The JESD204BRX block checks the k28.5 characters and checks CGS_ERR signal for any errors.
  6. Once JESD204BRX block receives atleast four k28.5 characters, Code Group Synchronization (CGS) is complete and TB_SYNC_N is deasserted.
  7. After the successful completion of the CGS phase, the JESD204BTX block starts the ILA sequence by transmitting four multi-frames in the following sequence:
    • First frame at TB_TX_SOMF = 0x8
    • Second frame at TB_TX_SOMF = 0x2
    • Third frame at TB_TX_SOMF = 0x8
    • Fourth frame at TB_TX_SOMF = 0x2fter the transceiver block is initialized, the TB_RX_READY signal is asserted high.
  8. The JESD204BRX link starts receiving four multi-frames in the following sequence:
    • First frame at TB_TX_SOMF = 0x8
    • Second frame at TB_TX_SOMF = 0x2
    • Third frame at TB_TX_SOMF = 0x8
    • Fourth frame at TB_TX_SOMF = 0x2

    The ILA phase test passes if all JESD204BRX DATA_OUT is properly received with frame alignment.

  9. After successful completion of the ILA phase, the JESD204BTX block enters in to the data phase.
  10. This is indicated with RX_STATE signal of the CoreJESD204B Rx IP as 11. See JESD204B Handbook for more information.
  11. In the data phase, the following data is fed to the JESD204BTX block: PRBS7, PRBS15, PRBS23, and PRBS31 using the PRBS generator.
  12. Sine, Square, Saw, and triangular waves are generated from the waveform generator.
  13. The data checker checks the received PRBS pattern against the expected PRBS pattern.
  14. The waveform output can be viewed in the Simulation window on corresponding wave selection as shown in Figure 4-3.
  15. If no error is detected by the data checker, the testbench issues a TESTBENCH PASSED message stating that the simulation was successful. If an error is detected, the testbench issues a TESTBENCH FAILED message to indicate that the testbench has failed.

While the simulation is running, you can see the status of the test cases in the Transcript window of ModelSim.

After simulation, the Waveform window displays the simulation waveforms as shown in the following figure.

Figure 4-3. Simulation Waveform Window