1.5 Reset Circuit

SmartFusion 2/IGLOO 2 devices have a dedicated asynchronous Schmitt-trigger reset input pin (DEVRST_N) with a maximum ramp time not more than 1 µs. This active-low signal must be asserted only when the device is unresponsive due to some unforeseen circumstances. It is not recommended to assert this pin during a programming (including eNVM) operation, as it may cause severe consequences including corruption of the device configuration. Asserting this signal tristates all user I/O and resets the system. Deasserting DEVRST_N enables the system controller to begin its startup sequence.

The following figure shows an example of a reset circuit using the Maxim DS1818 reset device, which maintains reset for 150 ms after the 3.3V supply returns to an in-tolerance condition. Adding a capacitor to ground on DEVRST_N avoids high-frequency noise and unwanted glitches that could reset the device.

Important: Use DEVRST_N only for IAP or auto update. Do not use DEVRST_N for user logic reset.
Figure 1-7. Reset Circuit

If the reset device is not used, DEVRST_N must be pulled up to VPP through a 10 kΩ resistor, as shown in the following figure.

Figure 1-8. Without Reset Circuit

If the user logic needs to be reset, any FPGA I/O can be used as an asynchronous reset for the user logic, as shown in the following figure.

Figure 1-9. Fabric Logic Reset

Use the fabric logic reset for CM3 Reset, fabric logic reset, MSS reset (including all peripherals), FDDR reset, and SerDes reset. For more information about fabric reset, see SmartFusion2 MSS DDR Controller Configuration Guide.